Plenty to keep you busy this month.  Lots of RAKs, videos, and new Quick Start Guides and FAQs.

Application Notes

1. Using Annotation Browser with Virtuoso IPVS

Learn how to invoke the Annotation Browser and have it always appear docked to a specific location of the layout window, how to customize the Annotation Browser, and how to automatically set the visibility of the error markers.

2. AMS Designer INCISIVE Command-line Flow Use Model (updated)

Provides an overview on how to run mixed-signal simulations from the command line using the irun command.

3. Spectre PSPICE Netlist Support

Provides a means for designers to analyze IC and PCB components together in the same simulation by including PCB components in PSPICE format into a Spectre integrated circuit simulation.

Rapid Adoption Kits

4. Analog Design Environment XL (ADE XL) Workshop (updated)

Virtuoso Analog Design Environment XL provides a multi-test simulation environment for thorough design validation, extensive design exploration, IP reuse, and early insight into manufacturing variability. This material has been designed to highlight many of the features as well as key functionality of ADE XL. Includes new features in ADE XL up through IC 6.1.6 ISR6.

5. Virtuoso Visualization and Analysis (ViVA) (updated)

The Virtuoso Visualization and Analysis tool is an analog/mixed-signal waveform viewer providing the means to thoroughly analyze the data generated by circuit simulation. Learn how to use it either as a standalone tool or as an integrated part of the Virtuoso Analog Design Environment (L and XL). Includes new features in ViVA up through IC 6.1.6 ISR6.

6. MODGEN

Module generators are designed to provide a way to generate multiple Pcell instances into a complex, highly matched, structured array. With the Modgen tool, you specify the devices to be arrayed, then specify an interdigitation pattern, and insert dummy devices, body contacts, and guard rings. Finally, you control the routing style and generate internal routing geometry.

7. Virtuoso IPVS

Virtuoso IPVS is a mechanism where the PVS verification tool is tightly integrated with the Virtuoso platform. This RAK includes an introduction to Virtuoso IPVS and covers how to get started, the different modes of Virtuoso IPVS, how DRC violations are created and displayed for each mode, and how to customizde the rules for your design.

8. Static and Dynamic Checks (updated)

This material describes the usage of the Spectre APS/XPS static and dynamic design checks available in MMSIM13.1.1. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues or connectivity problems. While the static checks are basic topology checks, the dynamic checks are performed during a Spectre APS/XPS transient simulation.

9. Introduction to Device Safe Operating Area (SOA), Circuit Conditions, and Asserts Workshop

This material highlights some of the ways that the user can set up and check for circuit conditions, perform device checking, and handle operating regions checks.

10. Mismatch Contribution

Mismatch Contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify the identified devices in the design to make the design less sensitive to device mismatch variation.

Videos

11. Shortcuts to Improving Productivity Series

A three-video series describing shortcuts for improving productivity in Virtuoso Schematic Editor (VSE).  Includes Editing Canvas (tips for quicker schematic drawing and editing), Customization, and Setting Colors and Backgrounds.

12. IC6.1.6 Pin-to-Trunk Block-Level Routing Series

A three-video series describing pin-to-trunk block-level routing.  Includes Basics, Using Pin-to-Trunk Routing to Route Between Blocks, and Pin-to-Trunk Routing Using the Finish Trunks Command.

13. IC6.1.6 Pin-to-Trunk Device-Level Routing Series

A four-video series describing pin-to-trunk device-level routing.  Includes Basics, Pin-to-Trunk Routing with Wire Assistant Overrides, Pin-to-Trunk Routing with Routing Scope and Via Control, and Pin-to-Trunk Routing Using the Finish Trunk Command.

Blogs

14. What's New(-ish) in ADE XL in IC616 ISR3?

Discusses new features in ADE XL in IC6.1.6 ISR3, including the ability to more easily debug individual Monte Carlo sample points, adding user-defined columns to the outputs tables, more efficient use of disk space, and performance improvements.

15. Keeping Your Circuit in Tune: Sensitivity Analysis and CIrcuit Optimization

Gives an overview of how to use sensitivity analysis and circuit optimization in Virtuoso Analog Design Environment GXL (ADE GXL) to efficiently tune your circuit over corners and statistical variation.

16. What's New in Virtuoso ADE XL in IC616 ISR6?

Discusses new features in ADE XL in IC6.1.6 ISR6, including corner export/import to CSV, creation of K-sigma corners from Monte Carlo results, the ability to add user notes, cancelling selected tests and corners, and value-based statistical corner creation.

Support and Documentation

17. Cadence Online Support Release Highlights

Describes recent enhancements to the Case Creation Pages and Design IP Email interface.

18. FAQs and Quick Start Guides added to the Virtuoso IC 6.1.6 documentation set

The following documents have been added or updated in various IC6.1.6 ISRs to supplement the existing Virtuoso documentation set. They cover a range of topics including FAQs, Quick Start Guides, and process flow information for particular product areas.

• Pcell IDE - Quick Start Guide (added in IC6.1.6ISR5 release)
• SKILL IDE Developer's Quick Start Guide (added in IC6.1.6ISR5 release)
• Virtuoso Schematic Editor - Productivity Shortcuts (added in IC6.1.6ISR3 release)
• Virtuoso Fluid Guard Ring Frequently Asked Questions (added in IC6.1.6ISR5 release)
• Virtuoso Quick Start:Virtuoso Floorplanner Flow (updated in IC6.1.6ISR3 release)
• Virtuoso Layout Suite L Frequently Asked Questions (added in IC6.1.6ISR6 release)
• RelXpert in ADE - Quick Start Guide (added in IC6.1.6ISR6 release)

19. How to turn on AMS UNL in IC 616 ISR6

The new AMS Unified Netlister (AMS UNL) was released in IC 6.1.6 ISR6.  Here's how to enable it.

Application Notes

1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40) LVS

Shows you how to put in place the PVS(LVS)-QRC(av_extracted) view using TSMC files.

Videos

2. Mismatch Contribution in Virtuoso Analog Design Environment GXL

Mismatch contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify the identified devices in the design to make the design less sensitive to device mismatch variation in IC 6.1.6.

Rapid Adoption Kits

3. Substrate/Well Connectivity Extraction

The substrate/well connectivity enhancements were made in VLS XL to help designers work more effectively on designs at lower geometry nodes.This RAK steps through the Extractor capabilities -- detecting short on a same substrate, creating isolated substrate and how to break a propagated connectivity on the same layer based on a generic 90nm PDK. IC6.1.6 ISR5

4. Making a layout XL-compliant using Update Binding (XLME)

Often layout engineers have existing or legacy layouts that they wish to use in VLS XL to take advantage of the connectivity-driven flow. With the introduction of the Update Binding functionality in IC6.1.6, it is now possible to quickly make a legacy layout fully XL-compliant.  IC6.1.6 ISR6.

5. Routing Constraint Interoperability - AoT Flow (Analog on Top)

This workshop demonstrates the capability to capture routing constraints in either Virtuoso or Encounter Digital Implementation System, propagate routing constraints across hierarchical boundaries, perform routing (using NanoRoute and the Virtuoso Wire Editor) while honoring constraints, and validate the routing results against the original routing constraints using PVS-cv. EDI 13.2 and Virtuoso IC6.1.5 ISR17.

6. Custom Digital Placement

The Custom Digital Placer is used to implement small digital designs with several thousand placeable components.  The Custom Digital Placer can also be used to place a few transistor-level devices along with standard cells (mixed mode).  IC6.1.6 ISR6

7. IC6.1.6 VSR ASIC Power and Signal Block-Level Autorouting Flow

This RAK steps through the power routing and signal routing of block-level stdcell ASIC flow.  IC6.1.6 ISR6.

8. Virtuoso Floorplanner Flow

This RAK steps thorugh the Floorplanner Flow in Virtuoso IC6.1.6 ISR5. The objective of this flow is to increase layout productivity through improved floorplanner functionality aimed at block-level interconnect. 

9. Virtuoso Analog Auto Placer

This RAK demonstrates the steps to use the Analog Placer in Virtuoso IC6.1.6 ISR5. This does automatic constraint-based placement. We will explore different placement modes like Quick Placement, Automatic Placement (more compact), and Place Like Schematic.

10. Voltus-Fi EMIR Analysis Workshop

This workshop will take you through IR-drop and electromigration analysis flow utilizing our patent-pending technology in MMSIM (APS/XPS) followed by visualization of results in Virtuoso Layout Editor.  IC6.1.6 ISR6 and MMSIM13.1 ISR3.

11. Sample Pcells Abutment

This RAK steps through the pcell abutment in Virtuoso IC6.1.6 ISR6.The objective of this document is to illustrate setting up the pcell abutment using the different properties with Cadence default abutment code and using custom abutment function.

Blogs

12. High-Yield Analysis and Optimization -- How to Design the Circuit to Six Sigma

Discusses the methodology and algorithms in ADE GXL to perform high-yield estimation and six-sigma statistical corner creation to help meet high-yield requirements for memory design and other mission-critical applications.

13. How to Specify Phase Noise as an Instance Parameter in Spectre Sources (e.g. vsource, isource, Port)

Describes the new capability in MMISM 13.1 to specify phase noise as an instance parameter on Spectre sources. 

14. DAC 2014: 30+ Customer, Partner Presentations Now Available on Cadence.com

One of the busiest spots on the Design Automation Conference (DAC 2014) show floor was the Cadence Theater, which featured continuous customer and partner presentations over a three-day period June 2-4. These informal, half-hour presentations allowed engineers to learn about problems and solutions from other engineers, and to hear about the latest capabilities from Cadence ecosystem partners. Most of the Cadence Theater presentations are now available in the form of audiotapes and slides.

Solutions

15. How to stop popup of Distributed Processing Options Form

For users of ADE Distributed Processing, a few key environment variables for those popup haters out there. 

16. Information, Q&A on APS parasitic reduction: +parasitics and ++parasitics options

 Nice one-stop shop for information about what these options do and how to use them.

17. How is mismatch applied in array/parallel devices in Spectre Monte Carlo?

Important information about the way mismatch is handled for different types of device configurations. 

18. How to perform a stability (stb) analysis on a loop within an extracted view

Clever little trick to facilitate analyzing loop stability on post-layout designs.

19. Verilog Netlisting (Verilog Out): Quick Reference to Basics and Frequently Referred Solutions

 Handy document on Verilog netlisting with lots of useful links to extra information.

20. auCdl Netlisting of schematic: Quick Reference to Basics and Frequently Referred Solutions

Handy document on auCdl netlisting, usually used for LVS.  Lots of links to extra information.

21. SPICEIN: Quick Reference to Basics and Frequently Referred Solutions

Handy document on SpiceIn to import textual netlists (CDL, HSpice, Spectre, SPICE) and create either schematic or netlist views. 

Stacy Whiteman

Excuse the tennis analogy, but just coming out of Wimbledon!  However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take"  between the EDA world and the many universities around the world. At Cadence, we have an extensive University Program and, through the years, we have worked closely on everything from developing curriculum (using our software, of course) to engaging universities in specific research for us to assisting Ph.D. students with the work on their theses. In fact, the Design Automation Conference (DAC) has had a university arm from the earliest days of the conference. This brings me to the reason for this blog, to congratulate Carnegie Mellon University Ph.D. student Shupeng Sun for receiving  the newly established Best Poster Award at the ACM SIGDA Ph.D. Forum at this year's DAC in San Francisco. The poster focused on Sun's radically new statistical analysis methodology that will allow companies to produce better circuits in electronic devices.

The reason it is of particular interest to me is that the work was a collaborative project between CMU and Cadence. A number of Cadence researchers and developers also have been involved in the project, including engineering directors Hongzhou Liu and Ben Gu, and Kangsheng Luo, a senior member of the technical staff.

All electronics are made up of thousands or even millions of circuit blocks, each of which can contain thousands of transistors — and if one of these blocks fail, the electronic device will not function properly. As electronics become more complicated, more circuit blocks are needed, increasing the chance for failure.

"If you only have 10 circuit blocks, it is relatively easy to make all 10 work, but if you have one million circuit blocks, then it is more difficult to make all of them work," said ECE Associate Professor Xin Li, Sun's adviser and research colleague.

Before Sun's novel work, validating a circuit block involved running a computer simulation that produces sample circuit blocks. Each sample can take minutes to hours to simulate, and millions of samples are required for an accurate validation of a new design. This method is very costly because it can take a few weeks or months to run one validation. And if the original design does not work, a second validation must be run — an enormous problem if a circuit designer has a deadline. Because the simulation process is so laborious, most companies opt for a very simple, very inaccurate estimation.

Sun developed an algorithm that calculates the failure rate and accounts for variability and uncertainties in the manufacturing process, allowing companies and researchers to run significantly fewer simulations. This new statistical methodology, referred to as Scaled-Sigma Sampling (SSS), requires producing only a few hundred or thousand samples.

"A few of the world's top semiconductor companies are already evaluating this new algorithm, and we are in the process of integrating it with our commercial product, Virtuoso ADE GXL," said Glen Clark, vice president of R&D for Cadence. "This is a great example of how a university and an EDA company can work together to deliver innovative solutions for the challenging problem of memory circuit yield."

Working collaboratively with universities has been a hallmark of Cadence, and we look forward to many more interesting and fruitful adventures together. I wonder if that is what Federer said to Djokovic when they shook hands across the net?  Congrats all around.

Steven Lewis 

Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose of browsing today.

Application Notes

1. Cadence Online Support Release Highlights

New features for searching and filtering, viewing cases and providing feedback

2. Generic Process Design Kit Downloads 

Get the latest versions of the Cadence Generic Process Design Kits (GPDK) and standard cell reference libraries, which are provided for use with Cadence Design Tools and Flows of Virtuoso and Encounter products. They are intended to be representative of actual semiconductor process.

3. Exchanging OA Database Views between Encounter (EDI) and Virtuoso (IC)

Talks about the basic things to know when interoperating between Encounter and Virtuoso for doing Analog-on-Top or Digital-on-Top design.

4. AMS Supply-Sensitive Connect Modules Application Note

Supply-sensitive connect modules offer a way to cleanly and accurately handle analog-to-digital and digital-to-analog conversion in analog/mixed-signal circuits involving multiple supplies and multiple voltages (MSMV).  This document provides multiple examples of how to implement this functionality.

5. Cadence Licensing FAQ

Compact presentation of the mostly frequently asked questions (and answers) to customer support regarding licensing.

6. Dongle Installation

How to set up Cadence licensing using USB dongles.

7. Layout Enhancements in IC6.1.6 ISR7 and ICADV12.1 ISR9

Describes new layout functionalities in the areas of Creating/Editing, Object Selection cycling, Copy/Move mirroring, Via Generation, Cloning, virtual connection and hierarchical extraction from selected instances.

8. Creating Batch Triggers in PVS

How to set up pre- and post- triggers from the Virtuoso GUI environment to perform various tasks before or after a PVS run.

Videos

9. Creating Pad Ring using Power Router

This video demonstrates how to create Pad routes using Power routing GUI in Virtuoso and save routing schemes for future use. It also shows SKILL rtePowerRoutePadRing command that can be used instead of GUI approach.

10. Introduction to Customer Support

Lots of great information about how to be more effective in using http://support.cadence.com.  Plus male AND female computer voices.

11. Modgen ECO Methodologies

Covers how to update Modgen constraints after device or constraint parameters have been updated in the schematic, and how to update the constraint view with Modgen changes made in the layout view.

12. New Features in SimVision 14.1 Release

Covers Driver tracing enhancements, Schematic Tracer, UVM and RTL Debug and other ease-of-use enhancements.

Rapid Adoption Kits

13. PLL Verification Workshop

Detailed workshop demonstrating different methods of characterizing PLL's and their principal components. 

14. Using VEC and VCD Files in AMS and Analog Simulation in ADE

Explains (and walks through) how to use digital stimulus (VCD, EVCD and VEC) files in AMS simulation with Spectre/Ultrasim as the analog solver.

15. Statistical Analysis

Demonstrates features of ADE XL and ADE GXL to perform Monte Carlo analysis, create fast K-sigma statistical corners and use circuit optimization to tune design performance and improve circuit yield.

16. Layout Design in IC6.1.6

Basics of using the Virtuoso Layout Suite, updated for IC6.1.6 ISR6.

17. Electrically Aware Design (EAD) Worskhop

EAD allows extraction of layout parasitics at any arbitrary point in a design cycle, including parasitic resimulation and electromigration analysis.  Updated for IC6.1.6 ISR7.

Blogs

18. Voltus-Fi Custom Power Integrity Solution: Electromigration and IR Drop at the Transistor Level

Introduces Cadence's new tool which provides transistor-level electromigration and voltage drop analysis with foundry-certified SPICE accuracy.

19. Quantus QRC Extraction Solution -- Massive Parallelism Extracts Accurate Parasitics Quickly

Introduces Cadence's release of a next-generation parasitic extraction tool that leverages massive parallelism to deliver up to 5X faster turnaround time.

20. EDA Plus Academia: A Perfect Game, Set and Match

Well-deserved kudos for collaborative research between Carnegie Mellon University and Cadence on a radically new statistical analysis methodology which won the newly established Best Poster Award a the ACM SIGDA Ph.D. Forum at this year's DAC.

Stacy Whiteman

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. You can also compare the relative importance of the contributing instances.  The analysis results can aid in making design changes to reduce the variation.  Mismatch Contribution is a variance-based global sensitivity analysis ^[1].

Mismatch Contribution is launched from Monte Carlo results.

 Here is a flat view of the outputs, and mismatch parameters are displayed and sorted by the swing specification.

Each device instance may be modeled with multiple statistical mismatch parameters.  The parameter names themselves are not always of interest.  In some cases the PDK models are derived from principal components.  Mismatch Contribution provides a hierarchical view where the total contribution of all of the device parameters is displayed for each instance.  The hierarchical view reports the contributions by instance for quick identification of important instances.

Cross probing to the schematic is provided.  The schematic is opened to the same level of hierarchy, and the selected instances are highlighted.  Navigate the table as you would a schematic.  Descend into a row (instance) of the table until reaching the leaf level.  The leaf level again displays the individual mismatch parameters of the instance.

By contrast, a top-level view with four blocks shows the block contributing the most variation of the specification.  Descend to find the lower-level contributors.

When global process variation is applied during the Monte Carlo analysis, the contributions from the process parameters are included in the contribution analysis.

Mismatch Contribution is not limited to linear effects.  When a linear model of the data is insufficient, a quadratic model is automatically applied.  The R^2 value in the header of the table for each specification is the proportion of variance explained by the model.  This is the goodness of fit of the model.  Sparse regression techniques allow for computation of the contributions even when the number of parameters is very large compared to the number of Monte Carlo samples simulated ^[2].

Mismatch Contribution is available now in Virtuoso ADE GXL, first released in IC6.1.6 ISR3.

[1] http://en.wikipedia.org/wiki/Variance-based_sensitivity_analysis 
[2] J. Tropp and A. Gilbert, "Signal recovery from random measurements via orthogonal matching pursuit," IEEE Trans. Information Theory, vol. 53, no. 12, pp. 4655--4666, 2007.

Lorenz Neureuter

Development Model for ADE and ViVA

Virtuoso Analog Design Environment (ADE) and ViVA follow a development model that allows new content to be added in every third ISR.  These content ISRs receive additional usability testing, product validation, and demonstrations and beta testing with customers. This development model gives R&D long enough development cycles to add meaningful content while ensuring that quality and stability of the main ISR stream is not compromised.

While this development model provides an excellent method to deploy new features and functionality in a frequent but controlled manner, it also presents challenges in making customers aware of the new capabilities.  This blog post outlines some of the new features that first appeared in ISR 3, which was released in November (hence the "-ish" in the blog title).  The next content release, ISR 6, will be available at the end of April so look for a fresh post with additional new items soon.

So let's get too it!  What's New(-ish) in ADE XL in 616 ISR 3?

• Performance and stability improvements when working with a large number of corners
• Better handling of disk full and other conditions which previously resulted in crashes
• Usability improvements in Annotation Balloons based on user feedback
• Ability to add user defined columns in ADE XL outputs setup and results table
• Allowing individual ICRP processes to be stopped and resubmitted
• Improved error debugging and access to job log
• Setting default results view for single run, sweeps and corners
• Measurements tied more tightly to analyses
• Improved use model for pre-run scripts
• More efficient use of disk space when a netlist is re-used for all points
• Low Discrepancy Sequence (LDS) sampling method support for Monte Carlo
• Ability to launch Debug Environment for Monte Carlo points
• Sample points displayed on histograms with cross selection to ADE XL results table

What new feature are you most excited to see?  Are there other features that you would like to have to make your job easier?  Do you have questions about ADE XL or other Virtuoso products?  Leave a comment  below and I will try to address them in future blog posts.  Also watch this space for details about new features in ISR 6 when it is released at the end of the month.

Tom Volden

Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL.

Application Notes

1. Physical Verification Checks and Generic Tips

Concise overview explaining the basics of the various DRC and LVS checks in rules files.

2. Recommendations and Tips for the PVS DRC Flow

Includes sections on preparation of runsets, running DRC, preparation of design blocks and DRC/LVS check of top-level GDS.

3. Recommendations and Tips for the PVS LVS Flow

Design and runset preparation, links to helpful solutions and sources of common errors.

4. Recommendations and Tips for the PVS Metal Fill Flow

Preparation of runsets, working with different fill scenarios and how to correct errors.

Rapid Adoption Kits

5. Making a layout XL-compliant using Update Binding (XLME)

Uses a sample design scenario to explain how the Update Binding command can be used to increase the VLS XL-compliance of a design using the physical connectivity in the layout and the output from a PVS LVS run. 

6. PSPICE netlist support in ADE

Describes the integration support in Analog Design Environment (ADE) to include a netlist in PSPICE format.

Solutions

7. Why isn't there an hbxf in the Choosing Analyses form?

You have recently started using the GUI for hb analysis and the associated small signal analyses. You noticed that there is a periodic xf (pxf) small signal analysis for pss. Why isn't there a similar analysis (hbxf) for hb?  Click on the link to find out.

8. Is PSF-XL supported for AMS simulation?

(Spoiler Alert) Why yes.  Yes it is.  This solution will tell you how to use this faster analog waveform format. 

9. Why do we have mulitple MMSIM13.1 hotfixes on downloads?

Several MMSIM 13.1 hotfix versions are being maintained on downloads to accommodate specific foundry/PDK rollouts.  Click the link for more information.

10. How to create a form showing a thumbnail image of the cellView

Wow, this could be fun.  A while ago, I wrote an article about how to create thumbnail images.  Now you can find out how to include those images in your own forms.

11. Does bindkey work with forms?

This solution provides an example of how to create a form in which you can register your own set of bindkeys.

12. How to create a custom RAP generator that creates additional constraints?

I would like to modify the existing CurrentMirror generator code to create additional constraints, for example, orientation and matched parameter constraints in addition to the modgen constraint. Here is that sample code.

Blogs

13. Fast Yield and Statistical Corners

Describes the different sampling methods available in ADE XL Monte Carlo analysis, the advantages of using auto-stop if you don't know how many samples are needed, and the types of statistical corners that can be created from the Monte Carlo results to help the designer improve circuit yield.

14. Efficient Design Migration Using Virtuoso Analog Design Environment GXL

The article provides an overview of a methodology for performing process migration for schematics and testbenches, including PDK and design assessment, design migration and final verification.

15. Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. The article describes the concepts behind this analysis how to use it.

Stacy Whiteman

Anyone who has ever played a musical instrument knows how hard it can be to keep the instrument in tune when subjected to variations in weather conditions. Heck, in 2009, Yo-Yo Ma and friends (sorry, he gets top billing because I used to play the cello) pantomimed their performance at the Presidential Inauguration because their instruments wouldn't function properly in the frigid temperatures. Guess they didn't want to risk sounding like my seventh-grade orchestra in front of that large an audience. 

Well, we've been talking a lot in this blog recently about the problems caused by the effects of variation on circuit design, and the risks of being "out of tune" can be just as great when it means your chip is late or doesn't work properly.

• How to sort through hundreds of combinations of PVT corners to find the ones that really matter
• How to efficiently analyze and design across statistical process and mismatch variation
• How to smoothly migrate a design from one process node to another while maintaining circuit performance
• How to quickly identify which parts of the circuit to tweak so statistical mismatch effects won't throw your design out of spec

Today we're going to talk about some of the features available in the Virtuoso Analog Design Environment GXL (ADE GXL) to help you tune your circuit to overcome the effects of variation on circuit performance. Let's start by putting things in the context of an overall flow that looks like this:

Setup and Corner Creation

The basic idea here is that you start with a test setup in ADE XL, which can consist of multiple testbenches, each with a set of output measurements and design specifications. Then you add the relevant corners, which will cover the limits of the design performance across which you need to optimize. These can be your standard PVT corners, they can be a critical subset of corners generated using the ADE GXL Worst Case Corners analysis, or they can be statistical corners generated from a Monte Carlo analysis to capture 3-sigma or other outlying statistical behavior for each of your design specifications. 

Parameterization

One of the keys to getting the most out of the circuit-tuning capabilities in ADE XL and ADE GXL is device parameterization. I've written about this feature before, but to recap, the Variables and Parameters Assistant in ADE XL allows you to create parameters for any device properties and vary them at will without having to edit the schematic. You can also incorporate critical device matching and ratioing relationships. 

The "Create Parameter Range" option will automatically create a +/-% range on any parameters, which makes sensitivity analysis and optimization a snap.

Sensitivity Analysis

Sensitivity Analysis in ADE GXL allows you to get a good idea of the criticial devices in your circuit and their effects on design performance. With only a few targeted simulations, you can find out which devices in your circuit have the most impact on each of your design specifications, as well as how changing a device size whether changing a device size to improve one spec will adversely change the other specs.  Device parameterization makes it quick and easy to evaluate "what-if" scenarios until your desired performance is achieved.

Local and Global Optimization

The optimization algorithms in ADE GXL have been proven within our customer base for many years. The optimizer works across all the multiple testbenches, specifications, and corners you already have set up, including the worst-case PVT and statistical corners you have defined to capture the extreme boundaries of your circuit behavior. Device parameters are intelligently varied over the ranges you have defined until all design specifications have been met. Simulations are distributed using ADE XL's job distribution system to maximize the efficiency of the analysis.

ADE GXL provides four local optimization algorithms: BFGS (recommended for most common analog circuits), Conjugate Gradient, Brent-Powell, and Hooke-Jeeves. Use these when you have a reasonable degree of confidence in your initial circuit starting point values. If you aren't sure of your starting point, use Global Optimization, which will perform a much broader exploration of the design space to find viable circuit solutions.

Several additional optimization-based run modes are available, including Size Over Corners to efficiently optimize over a large number of corners and Improve Yield, which combines Monte Carlo analysis and automatic statistical corner creation with iterations of circuit optimization to center your design within statistical process and mismatch variation.

Verification

"The proof of the pudding", as they say, "is in the eating," so the final step in our big red PowerPoint SmartArt arrow above is to verify the results of the circuit tuning. This may involve running a final simulation across all PVT corners or a final Monte Carlo analysis to verify the optimized design can overcome the effects of all types of variation.

In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3.  Here are more new features that are now available in Virtuoso ADE XL in the recently released ISR6.

• Notes can be added to tests, variables, corners, parameters, and histories. This allows you to document information about important items in your setup or make notes about a particular history to document simulation conditions, results, or other key information.
• Comma separated value (CSV) files can now be used to import and export corners setup. This improves the use model for managing corner setups in external editors. Prior to this enhancement, import/export required the use of more complicated XML format from the Virtuoso ADE XL setup database (SDB).
• Ability to cancel selected tests and corner points. Previously, stopping a run canceled all running and pending simulations. The new feature allows you to selectively cancel individual simulation for a particular corner or test. Remaining tests and corners will continue to be run.
• Creation of K-sigma corners from limited Monte Carlo samples. The new algorithm estimates the Probability Density Function and computes the corner specification value based on that PDF. A statistical corner that matches the target specification value is then created. This is an improvement over previous methods for creating statistical corners with a particular standard deviation as they required a large number of Monte Carlo points to achieve accurate results.
• Ability to filter evaluation and simulations errors from yield estimate in Monte Carlo simulations
• Wild card selection is now supported in the Annotation Setup form
• Value-based statistical corner creation from Monte Carlo simulation is available. This allows the distribution point to be maintained with minor changes to the design such as addition of new device instances. Prior to this, any changes to the design which impacted connectivity would invalidate the statistical corner.

What new feature are you most excited to see?  Are there other features that you would like to have to make your job easier?  Do you have questions about Virtuoso ADE XL or other Virtuoso products?  Leave a comment  below and I will try to address them in future blog posts.

Tom Volden

One failed memory cell out of millions cells will cause the whole memory circuit to fail without ECC (error checking and correction) techniques. That is why memory designers have high parametric yield requirements for the SRAM core cell. It requires no fails in hundreds of millions or billions of brutal force Monte Carlo simulations if foundry statistical models are accurate up to the high sigma region.Memory circuit designers also have high yield requirements for other circuit block and memory partitions, such as sense amplifier sor critical-path partitions.

How to analyze high yield and debug, improve the design in Virtuoso ADE

Virtuoso Analog Design Environment GXL selects WCD (worst case distance) metric-based method as its high yield solution. To estimate high yield, ADE GXL will first find the WCD point in the statistical space.Once the WCD point is found, the yield can be calculated directly using the WCD.

The accuracy of WCD is impacted by nonlinearity of spec boundary in statistical spaces. However, that error is not significant in most high yield applications. The WCD point has the shortest distance from nominal point to fail region in statistical space. It is also the most probable point to fail in statistical space. During a continuously running Monte Carlo process, the first failing Monte Carlo point has a very high probability to be very close to the WCD point in statistical space.This makes the WCD point very attractive for creating a high-yield statistical corner because it captures the circuit condition with the highest probability to fail.This point becomes increasingly important if designers want to debug and improve the design. Based on the WCD point, Virtuoso ADE GXL provides the capability to create a high-sigma corner to improve the yield. 

The completed high yield solution in Virtuoso ADE GXL is a part of the TSMC AMS reference flow. It includes:

1.    High yield calculation

2.    Creation of high yield statistical corner

3.    Optimization of the design with high yield corner

4.    Verification of design using high yield calculation

What is coming next? New algorithms for high dimension!

Cadence R&D co-invented the next-generation high yield estimation algorithm with researchers from Carnegie Mellon University recently[1]. The scaled-sigma sampling algorithm works well with high-dimensional nonlinear problems, which exist in large circuit blocks. Please stay tuned!. The algorithm will be publicly available in the coming IC616ISR release.

[1] Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo and Ben Gu, "Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 478-485, 2013.

Plenty to keep you busy this month.  Lots of RAKs, videos, and new Quick Start Guides and FAQs.

Application Notes

1. Using Annotation Browser with Virtuoso IPVS

Learn how to invoke the Annotation Browser and have it always appear docked to a specific location of the layout window, how to customize the Annotation Browser, and how to automatically set the visibility of the error markers.

2. AMS Designer INCISIVE Command-line Flow Use Model (updated)

Provides an overview on how to run mixed-signal simulations from the command line using the irun command.

3. Spectre PSPICE Netlist Support

Provides a means for designers to analyze IC and PCB components together in the same simulation by including PCB components in PSPICE format into a Spectre integrated circuit simulation.

Rapid Adoption Kits

4. Analog Design Environment XL (ADE XL) Workshop (updated)

Virtuoso Analog Design Environment XL provides a multi-test simulation environment for thorough design validation, extensive design exploration, IP reuse, and early insight into manufacturing variability. This material has been designed to highlight many of the features as well as key functionality of ADE XL. Includes new features in ADE XL up through IC 6.1.6 ISR3.

5. Virtuoso Visualization and Analysis (ViVA) (updated)

The Virtuoso Visualization and Analysis tool is an analog/mixed-signal waveform viewer providing the means to thoroughly analyze the data generated by circuit simulation. Learn how to use it either as a standalone tool or as an integrated part of the Virtuoso Analog Design Environment (L and XL). Includes new features in ViVA up through IC 6.1.6 ISR3.

6. MODGEN

Module generators are designed to provide a way to generate multiple Pcell instances into a complex, highly matched, structured array. With the Modgen tool, you specify the devices to be arrayed, then specify an interdigitation pattern, and insert dummy devices, body contacts, and guard rings. Finally, you control the routing style and generate internal routing geometry.

7. Virtuoso IPVS

Virtuoso IPVS is a mechanism where the PVS verification tool is tightly integrated with the Virtuoso platform. This RAK includes an introduction to Virtuoso IPVS and covers how to get started, the different modes of Virtuoso IPVS, how DRC violations are created and displayed for each mode, and how to customizde the rules for your design.

8. Static and Dynamic Checks (updated)

This material describes the usage of the Spectre APS/XPS static and dynamic design checks available in MMSIM13.1.1. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues or connectivity problems. While the static checks are basic topology checks, the dynamic checks are performed during a Spectre APS/XPS transient simulation.

9. Introduction to Device Safe Operating Area (SOA), Circuit Conditions, and Asserts Workshop

This material highlights some of the ways that the user can set up and check for circuit conditions, perform device checking, and handle operating regions checks.

10. Mismatch Contribution

Mismatch Contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify the identified devices in the design to make the design less sensitive to device mismatch variation.

Videos

11. Shortcuts to Improving Productivity Series

A three-video series describing shortcuts for improving productivity in Virtuoso Schematic Editor (VSE).  Includes Editing Canvas (tips for quicker schematic drawing and editing), Customization, and Setting Colors and Backgrounds.

12. IC6.1.6 Pin-to-Trunk Block-Level Routing Series

A three-video series describing pin-to-trunk block-level routing.  Includes Basics, Using Pin-to-Trunk Routing to Route Between Blocks, and Pin-to-Trunk Routing Using the Finish Trunks Command.

13. IC6.1.6 Pin-to-Trunk Device-Level Routing Series

A four-video series describing pin-to-trunk device-level routing.  Includes Basics, Pin-to-Trunk Routing with Wire Assistant Overrides, Pin-to-Trunk Routing with Routing Scope and Via Control, and Pin-to-Trunk Routing Using the Finish Trunk Command.

Blogs

14. What's New(-ish) in ADE XL in IC616 ISR3?

Discusses new features in ADE XL in IC6.1.6 ISR3, including the ability to more easily debug individual Monte Carlo sample points, adding user-defined columns to the outputs tables, more efficient use of disk space, and performance improvements.

15. Keeping Your Circuit in Tune: Sensitivity Analysis and CIrcuit Optimization

Gives an overview of how to use sensitivity analysis and circuit optimization in Virtuoso Analog Design Environment GXL (ADE GXL) to efficiently tune your circuit over corners and statistical variation.

16. What's New in Virtuoso ADE XL in IC616 ISR6?

Discusses new features in ADE XL in IC6.1.6 ISR6, including corner export/import to CSV, creation of K-sigma corners from Monte Carlo results, the ability to add user notes, cancelling selected tests and corners, and value-based statistical corner creation.

Support and Documentation

17. Cadence Online Support Release Highlights

Describes recent enhancements to the Case Creation Pages and Design IP Email interface.

18. FAQs and Quick Start Guides added to the Virtuoso IC 6.1.6 documentation set

The following documents have been added or updated in various IC6.1.6 ISRs to supplement the existing Virtuoso documentation set. They cover a range of topics including FAQs, Quick Start Guides, and process flow information for particular product areas.

• Pcell IDE - Quick Start Guide (added in IC6.1.6ISR5 release)
• SKILL IDE Developer's Quick Start Guide (added in IC6.1.6ISR5 release)
• Virtuoso Schematic Editor - Productivity Shortcuts (added in IC6.1.6ISR3 release)
• Virtuoso Fluid Guard Ring Frequently Asked Questions (added in IC6.1.6ISR5 release)
• Virtuoso Quick Start:Virtuoso Floorplanner Flow (updated in IC6.1.6ISR3 release)
• Virtuoso Layout Suite L Frequently Asked Questions (added in IC6.1.6ISR6 release)
• RelXpert in ADE - Quick Start Guide (added in IC6.1.6ISR6 release)

19. How to turn on AMS UNL in IC 616 ISR6

The new AMS Unified Netlister (AMS UNL) was released in IC 6.1.6 ISR6.  Here's how to enable it.

Stacy Whiteman

Application Notes

1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40) LVS

Shows you how to put in place the PVS(LVS)-QRC(av_extracted) view using TSMC files.

Videos

2. Mismatch Contribution in Virtuoso Analog Design Environment GXL

Mismatch contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify the identified devices in the design to make the design less sensitive to device mismatch variation in IC 6.1.6.

Rapid Adoption Kits

3. Substrate/Well Connectivity Extraction

The substrate/well connectivity enhancements were made in VLS XL to help designers work more effectively on designs at lower geometry nodes.This RAK steps through the Extractor capabilities -- detecting short on a same substrate, creating isolated substrate and how to break a propagated connectivity on the same layer based on a generic 90nm PDK. IC6.1.6 ISR5

4. Making a layout XL-compliant using Update Binding (XLME)

Often layout engineers have existing or legacy layouts that they wish to use in VLS XL to take advantage of the connectivity-driven flow. With the introduction of the Update Binding functionality in IC6.1.6, it is now possible to quickly make a legacy layout fully XL-compliant.  IC6.1.6 ISR6.

5. Routing Constraint Interoperability - AoT Flow (Analog on Top)

This workshop demonstrates the capability to capture routing constraints in either Virtuoso or Encounter Digital Implementation System, propagate routing constraints across hierarchical boundaries, perform routing (using NanoRoute and the Virtuoso Wire Editor) while honoring constraints, and validate the routing results against the original routing constraints using PVS-cv. EDI 13.2 and Virtuoso IC6.1.5 ISR17.

6. Custom Digital Placement

The Custom Digital Placer is used to implement small digital designs with several thousand placeable components.  The Custom Digital Placer can also be used to place a few transistor-level devices along with standard cells (mixed mode).  IC6.1.6 ISR6

7. IC6.1.6 VSR ASIC Power and Signal Block-Level Autorouting Flow

This RAK steps through the power routing and signal routing of block-level stdcell ASIC flow.  IC6.1.6 ISR6.

8. Virtuoso Floorplanner Flow

This RAK steps thorugh the Floorplanner Flow in Virtuoso IC6.1.6 ISR5. The objective of this flow is to increase layout productivity through improved floorplanner functionality aimed at block-level interconnect. 

9. Virtuoso Analog Auto Placer

This RAK demonstrates the steps to use the Analog Placer in Virtuoso IC6.1.6 ISR5. This does automatic constraint-based placement. We will explore different placement modes like Quick Placement, Automatic Placement (more compact), and Place Like Schematic.

10. Voltus-Fi EMIR Analysis Workshop

This workshop will take you through IR-drop and electromigration analysis flow utilizing our patent-pending technology in MMSIM (APS/XPS) followed by visualization of results in Virtuoso Layout Editor.  IC6.1.6 ISR6 and MMSIM13.1 ISR3.

11. Sample Pcells Abutment

This RAK steps through the pcell abutment in Virtuoso IC6.1.6 ISR6.The objective of this document is to illustrate setting up the pcell abutment using the different properties with Cadence default abutment code and using custom abutment function.

Blogs

12. High-Yield Analysis and Optimization -- How to Design the Circuit to Six Sigma

Discusses the methodology and algorithms in ADE GXL to perform high-yield estimation and six-sigma statistical corner creation to help meet high-yield requirements for memory design and other mission-critical applications.

13. How to Specify Phase Noise as an Instance Parameter in Spectre Sources (e.g. vsource, isource, Port)

Describes the new capability in MMISM 13.1 to specify phase noise as an instance parameter on Spectre sources. 

14. DAC 2014: 30+ Customer, Partner Presentations Now Available on Cadence.com

One of the busiest spots on the Design Automation Conference (DAC 2014) show floor was the Cadence Theater, which featured continuous customer and partner presentations over a three-day period June 2-4. These informal, half-hour presentations allowed engineers to learn about problems and solutions from other engineers, and to hear about the latest capabilities from Cadence ecosystem partners. Most of the Cadence Theater presentations are now available in the form of audiotapes and slides.

Solutions

15. How to stop popup of Distributed Processing Options Form

For users of ADE Distributed Processing, a few key environment variables for those popup haters out there. 

16. Information, Q&A on APS parasitic reduction: +parasitics and ++parasitics options

 Nice one-stop shop for information about what these options do and how to use them.

17. How is mismatch applied in array/parallel devices in Spectre Monte Carlo?

Important information about the way mismatch is handled for different types of device configurations. 

18. How to perform a stability (stb) analysis on a loop within an extracted view

Clever little trick to facilitate analyzing loop stability on post-layout designs.

19. Verilog Netlisting (Verilog Out): Quick Reference to Basics and Frequently Referred Solutions

 Handy document on Verilog netlisting with lots of useful links to extra information.

20. auCdl Netlisting of schematic: Quick Reference to Basics and Frequently Referred Solutions

Handy document on auCdl netlisting, usually used for LVS.  Lots of links to extra information.

21. SPICEIN: Quick Reference to Basics and Frequently Referred Solutions

Handy document on SpiceIn to import textual netlists (CDL, HSpice, Spectre, SPICE) and create either schematic or netlist views. 

Stacy Whiteman

Excuse the tennis analogy, but just coming out of Wimbledon!  However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take"  between the EDA world and the many universities around the world. At Cadence, we have an extensive University Program and, through the years, we have worked closely on everything from developing curriculum (using our software, of course) to engaging universities in specific research for us to assisting Ph.D. students with the work on their theses. In fact, the Design Automation Conference (DAC) has had a university arm from the earliest days of the conference. This brings me to the reason for this blog, to congratulate Carnegie Mellon University Ph.D. student Shupeng Sun for receiving  the newly established Best Poster Award at the ACM SIGDA Ph.D. Forum at this year's DAC in San Francisco. The poster focused on Sun's radically new statistical analysis methodology that will allow companies to produce better circuits in electronic devices.

The reason it is of particular interest to me is that the work was a collaborative project between CMU and Cadence. A number of Cadence researchers and developers also have been involved in the project, including engineering directors Hongzhou Liu and Ben Gu, and Kangsheng Luo, a senior member of the technical staff.

All electronics are made up of thousands or even millions of circuit blocks, each of which can contain thousands of transistors — and if one of these blocks fail, the electronic device will not function properly. As electronics become more complicated, more circuit blocks are needed, increasing the chance for failure.

"If you only have 10 circuit blocks, it is relatively easy to make all 10 work, but if you have one million circuit blocks, then it is more difficult to make all of them work," said ECE Associate Professor Xin Li, Sun's adviser and research colleague.

Before Sun's novel work, validating a circuit block involved running a computer simulation that produces sample circuit blocks. Each sample can take minutes to hours to simulate, and millions of samples are required for an accurate validation of a new design. This method is very costly because it can take a few weeks or months to run one validation. And if the original design does not work, a second validation must be run — an enormous problem if a circuit designer has a deadline. Because the simulation process is so laborious, most companies opt for a very simple, very inaccurate estimation.

Sun developed an algorithm that calculates the failure rate and accounts for variability and uncertainties in the manufacturing process, allowing companies and researchers to run significantly fewer simulations. This new statistical methodology, referred to as Scaled-Sigma Sampling (SSS), requires producing only a few hundred or thousand samples.

"A few of the world's top semiconductor companies are already evaluating this new algorithm, and we are in the process of integrating it with our commercial product, Virtuoso ADE GXL," said Glen Clark, vice president of R&D for Cadence. "This is a great example of how a university and an EDA company can work together to deliver innovative solutions for the challenging problem of memory circuit yield."

Working collaboratively with universities has been a hallmark of Cadence, and we look forward to many more interesting and fruitful adventures together. I wonder if that is what Federer said to Djokovic when they shook hands across the net?  Congrats all around.

Steven Lewis 

Apologies for skipping a month, but things got a bit hectic, so enjoy a double-dose of browsing today.

Application Notes

1. Cadence Online Support Release Highlights

New features for searching and filtering, viewing cases and providing feedback

2. Generic Process Design Kit Downloads 

Get the latest versions of the Cadence Generic Process Design Kits (GPDK) and standard cell reference libraries, which are provided for use with Cadence Design Tools and Flows of Virtuoso and Encounter products. They are intended to be representative of actual semiconductor process.

3. Exchanging OA Database Views between Encounter (EDI) and Virtuoso (IC)

Talks about the basic things to know when interoperating between Encounter and Virtuoso for doing Analog-on-Top or Digital-on-Top design.

4. AMS Supply-Sensitive Connect Modules Application Note

Supply-sensitive connect modules offer a way to cleanly and accurately handle analog-to-digital and digital-to-analog conversion in analog/mixed-signal circuits involving multiple supplies and multiple voltages (MSMV).  This document provides multiple examples of how to implement this functionality.

5. Cadence Licensing FAQ

Compact presentation of the mostly frequently asked questions (and answers) to customer support regarding licensing.

6. Dongle Installation

How to set up Cadence licensing using USB dongles.

7. Layout Enhancements in IC6.1.6 ISR7 and ICADV12.1 ISR9

Describes new layout functionalities in the areas of Creating/Editing, Object Selection cycling, Copy/Move mirroring, Via Generation, Cloning, virtual connection and hierarchical extraction from selected instances.

8. Creating Batch Triggers in PVS

How to set up pre- and post- triggers from the Virtuoso GUI environment to perform various tasks before or after a PVS run.

Videos

9. Creating Pad Ring using Power Router

This video demonstrates how to create Pad routes using Power routing GUI in Virtuoso and save routing schemes for future use. It also shows SKILL rtePowerRoutePadRing command that can be used instead of GUI approach.

10. Introduction to Customer Support

Lots of great information about how to be more effective in using http://support.cadence.com.  Plus male AND female computer voices.

11. Modgen ECO Methodologies

Covers how to update Modgen constraints after device or constraint parameters have been updated in the schematic, and how to update the constraint view with Modgen changes made in the layout view.

12. New Features in SimVision 14.1 Release

Covers Driver tracing enhancements, Schematic Tracer, UVM and RTL Debug and other ease-of-use enhancements.

Rapid Adoption Kits

13. PLL Verification Workshop

Detailed workshop demonstrating different methods of characterizing PLL's and their principal components. 

14. Using VEC and VCD Files in AMS and Analog Simulation in ADE

Explains (and walks through) how to use digital stimulus (VCD, EVCD and VEC) files in AMS simulation with Spectre/Ultrasim as the analog solver.

15. Statistical Analysis

Demonstrates features of ADE XL and ADE GXL to perform Monte Carlo analysis, create fast K-sigma statistical corners and use circuit optimization to tune design performance and improve circuit yield.

16. Layout Design in IC6.1.6

Basics of using the Virtuoso Layout Suite, updated for IC6.1.6 ISR6.

17. Electrically Aware Design (EAD) Worskhop

EAD allows extraction of layout parasitics at any arbitrary point in a design cycle, including parasitic resimulation and electromigration analysis.  Updated for IC6.1.6 ISR7.

Blogs

18. Voltus-Fi Custom Power Integrity Solution: Electromigration and IR Drop at the Transistor Level

Introduces Cadence's new tool which provides transistor-level electromigration and voltage drop analysis with foundry-certified SPICE accuracy.

19. Quantus QRC Extraction Solution -- Massive Parallelism Extracts Accurate Parasitics Quickly

Introduces Cadence's release of a next-generation parasitic extraction tool that leverages massive parallelism to deliver up to 5X faster turnaround time.

20. EDA Plus Academia: A Perfect Game, Set and Match

Well-deserved kudos for collaborative research between Carnegie Mellon University and Cadence on a radically new statistical analysis methodology which won the newly established Best Poster Award a the ACM SIGDA Ph.D. Forum at this year's DAC.

Stacy Whiteman

There has been a flurry of activity on COS over that past couple of months. I can't even come close to listing everything, but here are some of the highlights. Be sure to check out the "Training Bytes" section at the end of this post for information on a recent initiative in which Cadence training experts are publishing short video excerpts from our most popular classes.

Product Pages

0. Many of the product pages on COS have been enhanced to be more comprehensive so they can act as "hubs" for finding information on a particular product area. Just select "Product Pages->Select a Product" from the main COS landing page, then choose from the list of products and click on "View Product Details" to go to that page. Choose "Virtuoso Analog Design Environment" to access ADE L/XL/GXL information for IC6.X. Here you can get quick links to the ADE XL and ViVA Video Channels, relevant product documentation, the latest postings on the Custom IC Design Community Forum, and more.

Application Notes

1. Using Spectre to Simulate IBIS Models

IBIS is a fast and accurate behavioral method for modeling input and output buffers. This app note explains and demonstrates how to simulate IBIS models in Spectre circuit simulator.

2. Layout enhancements in IC6.1.6 ISR7 and ICADV12.1 ISR9

Describes new features for layout creation and editing, object selection, via generation, cloning, and more.

3. Implementing Open Access Pin Connectivity Model in SKILL Pcells

Describes how to create parameterized cells with pins defined as strong connect, weak connect, and must connect (and explains the differences).

4. Virtuoso Pin Connectivity Model

Describes the design objects and APIs used to define connectivity in Virtuoso Schematic Editor and Virtuoso Layout Editor. It explains how to create and access these objects through both SKILL and the GUI.

5. Demystifying NCELAB

This is an update on one of the most frequently downloaded documents on COS. It explains the errors that are most frequently encountered at the elaboration phase of running AMS Designer. Each error description includes an example testcase and the steps needed to resolve the error.

6. Spectre PSPICE Netlist Support

Walks through the new feature in MMSIM 14.1 that enables the user to include PCB components in PSPICE format into a Spectre simulation.

Rapid Adoption Kits (RAKs)

7. ADE Verification Workshop

The workshop demonstrates how to characterize an ADC using Spectre and the Virtuoso Analog Design Environment.

What you will learn: Evaluate ADC Effective Number of Bits, Dynamic Comparator Characterization, Capacitor D/A Converter Characterization, Clock Generator Characterization.

8. IC 6.1.6 Pin-to-Trunk Device-Level Routing

(Updated for IC 6.1.6 ISR8) This material steps through the Pin-to-Trunk Device-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at device-level interconnect. This flow enables users to quickly connect device pins in a structured topology.

What you will learn: Pin-to-Trunk Routing Basics, Pin-to-Trunk Routing with Wire Assistant Overrides, Pin-to-Trunk Routing with Routing Scope and Via Control.

9. IC 6.1.6 Pin-to-Trunk Block_Level Routing

(Updated for IC 6.1.6 ISR8) This material steps through the Pin-to-Trunk Block-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at block-level interconnect. This flow enables users to quickly connect block pins in a structured topology.

What you will learn: Pin-to-Trunk Routing Basics, Using Pin-to-Trunk Routing to Route Between Blocks.

10. Liberate AMS For Characterizing Mixed-Signal Blocks (Command-line Flow)

Static Timing Analysis (STA) on modern SoC designs includes paths that go through digital blocks embedded in AMS blocks. There is a need to generate accurate liberty (.lib) files for these AMS blocks that contain analog block pins that interface with digital blocks. Tools used for generating liberty files for standard cells, I/O, or memories cannot handle such blocks due to their large size, difficulties in handling the included analog circuitry, time required to run accurate simulations, etc. Liberate AMS is architected to characterize large macro blocks containing complex custom digital and analog components like PLLs, SerDes, data converters, etc., for timing, power, and noise.

What you will learn: Intro to Characterization of AMS IP Blocks, Characterization Terminology, Essential Liberty Syntax; Tool Overview, Setup for Characterization, Output Files, Debug, Troubleshooting.

11. Split Connect Rules

This example describes how you can use the Split Connect Modules (CM) in your design in the command line flow. By default, Merged Connect Modules (CM) are inserted in your design. So, you have to create either user-defined connect rules or different ie cards in order to use the Split Connect Modules.

What you will learn: Creating split connect rule in amsd block, Running Simulation and Checking Results, Checking connect rules/modules in the log file.

12. SDF Annotation flow for AMS Simulations from Virtuoso ADE

This material provides an overview about how to use the SDF file in the AMS simulation flow. The document provides the knowledge needed to annotate timing data to your Verilog designs and to understand the Standard Delay Format (SDF) for simulation and annotation purpose. It also explains some of the SDF keywords, discusses some issues you may encounter and demonstrates the annotation process.

What you will learn: General Introduction to SDF, Verilog SDF Annotation, Test case, Most frequent Errors and Warnings.

13. Voltus-Fi EMIR Analysis Workshop

This workshop covers the basics of Voltus-Fi-based transistor-level electromigration and IR-drop analysis. The flow is integrated with APS/XPS simulators that use a new technology designed to provide very high capacity and performance.

What you will learn: Running QRC to generate a good DSPF for EMIR analysis, setting up EMIR analysis options in ADE-L and XL, followed by analysis of results in Virtuoso Layout Editor. You will also learn about the key layout debugging capabilities of the Voltus-Fi solution.

14. Static and Dynamic Checks

This material describes the usage of the Spectre APS/XPS static and dynamic design checks available in MMSIM13.1.1. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues, and connectivity problems. While the static checks are basic topology checks, the dynamic checks are performed during a Spectre APS/XPS transient simulation.

What you will learn: Use model, Static check, Dynamic check

Solutions

15. Role of portOrder and CDF termOrder in Verilog and auCdl Netlisters

When we netlist a schematic, the ports or pins of a subckt or module are listed in a particular order. Different netlisters decide this order of pins in different ways. In this document, we are going to cover how OSS-based netlisters like auCdl and Verilog handle this pin order via CDF termOrder and portOrder property.

16. How to get an email sent to user after ADE XL simulation is completed

Contains an example of how you can connect a procedure with the runFinished trigger to send an email on completion of an ADE XL run.

17. How to run simulations diagnostics for a given time window or range?

New options in MMSIM 14.1 to limit the printing of simulation diagnostic information within a specified time range.

Videos

18. AMS Unified Netlist (UNL) Quick Start

Quick start video showing setup and usage of the new AMS UNL flow in the Virtuoso solution. All existing and new users to AMS ADE are strongly recommended to migrate to AMS UNL flow. This video is meant to aid in the immediate proliferation of the non-default, production status of AMS UNL. To use, setenv AMS_UNL=YES.

19. Compelling Advantages in Migrating your AMS OSS Netlisting Flow to the New AMS Unified Netlisting (AMS UNL) Flow

Present the seven main advantages in migrating your AMS OSSN flow to the new AMS UNL flow: 1) Retain use of SpectreCDF siminfo, 2) Enhanced irun binding engine, 3) Enhanced black-box design unit methodology, 4) Full VHDL/VHDL-AMS support, 5) Enhanced schematic/text bus handling, 6) Shadow-free text netlisting flow, 7) Symbol-free text netlisting flow.

20. Compelling Advantages in Migrating your AMS Cell-Based Netlisting Flow to the New AMS Unified Netlisting (AMS UNL) Flow

Present the three compelling advantages of migrating your AMS Cell-Based Netlisting Flow to the new AMS Unified Netlisting(AMS UNL) flow: 1) Use existing SpectreCDF siminfo without having to create and maintain ams siminfo, 2) Use irun single-step executable, 3) Ability to reference text cellviews external to Virtuoso by using the black-box design unit(BDU) methodology

21. Creating Pad/Core/Block Rings Using Power Router

A set of three videos demonstrating how to create pad, core, and block rings using the power routing GUI in the Virtuoso solution. Also shows SKILL commands that can be used instead of the GUI approach.

22. Back Annotation of Modgen Dummies

This video demonstrates how to create a Modgen constraint, add dummies, and back annotate the dummies to the schematic.

23. Bindkey and Access Keys - Features to Improve Productivity - An Overview

It shows the pane showing tools for which bindkey is defined. Format of a bindkey. How to add a bindkey. Duplicate bindkey warning. Access keys.

24. Distributed Processing in ADE L

It demonstrates "How to use Distributed processing from ADE L with LSF". It has been made on IC616ISR8.

Training Bytes

25->Very Large Number.

Did you see the latest video segments in the Video Library? Cadence course developers are now creating and sharing Training Bytes from their course materials. These short videos help you learn a task or topic in a few minutes. Go check them out in Video Library and send feedback via the Feedback box. There are way too many to list here individually, but this is a little taste (ha-ha, "bytes"—"taste", get it?).  I'm running out of time to add all the individual links, but you can find them all with a quick search or just select Resources->Video Library to see the full list.

1. From the course: Virtuoso Layout Pro
   1. Create Via Command
   2. Alignment Commands
   3. Using the Wire Editing Options with Create Wire
2. From the course: Virtuoso Layout for Advanced Nodes
   1. Double Patterning—Top-Level Shapes and Instances
   2. FinFET Folding
   3. Creating and Editing Guardrings in Advanced Node Technology

3. From the course: Virtuoso Layout Design Basics
   1. Brief Overview of Dynamic Display
   2. Overview and Demo on Creating Instances as Mosaics
   3. Overview of Selection Options Form
4. From the course: Virtuoso Analog Simulation Techniques
   1. Performing Corner Analysis in ADE XL
   2. Operating Region Checks in ADE XL
   3. Variables and Parameters in ADE XL

Happy New Year to all from the award-winning Virtuosity blog team (Alice, Praveena, Rajesh and myself)!  Okay, so it was an internal Cadence Standing Ovation Team Award, but it works for me.

There are few things I love more than learning and every month (or two) when I look through the new content, I am delighted to see how much high-quality material is available to highlight new features and help you use our software more effectively.

So without further ado...

1. Cadence Online Support Release Highlights: December 22, 2014

Application Notes

2. FGR Object Oriented Infrastructure: Class Hierarchy and Extensibility

The implementation of the Fluid Guard Ring solution resides in a SKILL object-oriented infrastructure. This consists of classes and their methods known as Virtuoso Fluid Object (VFO). The VFO infrastructure comprises specific class declarations that have a defined hierarchy. This document covers information about these classes, as well as information on how to define custom FGR PCell devices in the technology file.

3. Statistical Analysis Quick Start ADE XL/GXL

Monte Carlo sampling setup and post-processing, statistical corners, mismatch and variance contribution in ADE XL/GXL updated for IC6.1.6 ISR9 and ICADV12.1 ISR11.

4. What is New in Virtuoso Front End IC6.1.6 ISR9 and ICADV12.1 ISR11

New features in ADE L/XL/GXL and ViVA in Virtuoso IC6.1.6 ISR9 and ICADV12.1 ISR11.

5. Waveform Data Reduction and Compression Techniques

This document explores the various options available to analog/mixed-signal designers to reduce the waveform dump size and some post-processing techniques in the waveform viewers to improve the waveform viewing experience.

6. Virtuoso Stream Translator Enhancements in IC6.1.6 ISR9

Describes performance and usability improvements of Stream translation in Virtuoso IC6.1.6ISR9.

7. Analyzing XStream Performance Issues

This application note explains how to understand and improve runtime of Virtuoso streamIn and streamOut.

8. VLS XL - Extractor Verify substrate connectivity

VLS XL Connectivity Extractor supports the mature process nodes as well as the advanced process nodes (10nm, 14nm FDSOI...). This document provides guidelines on how to write the techfile in order to verify the substrate connectivity.

Videos

9. Removing Devices from Netlists

This video illustrates the different methods of removing devices from the netlist of a design, which is generated using an OSS-based netlister.

10. Automatic Extraction of Power Intent Using PIEA

This video shows using the Power Intent Extraction Options form for automatic extraction of power intent.

11. Job Policy Setup for Distributed Processing in ADE XL

This video demonstrates how to set job policy for distributed processing in ADE XL with LSF. It has been developed on IC6.1.6 ISR9.

12. Virtuoso Layout Suite: Improve hierarchical design editing performance using Area Display feature

Improve hierarchical design editing performance using the Area Display feature.

13. Out of Context Probing and Plotting in ADE L and ADE XL

Demonstrates how to do out-of-context probing from ADE.

14. Using DRD Compactor

This video provides an overview of DRD Compactor options.

15. Result Annotation Flow Enhancement in Virtuoso

This video demonstrates annotation set up revamp in IC 6.1.6, access of annotation, and the plotting menu from schematic editor and the annotation setup form.

16. Communication of SMG with VSE and amsDmv

Demonstrates SMG VSE sub-app feature and SMG-amsDmv Communication feature.

17. Comparing Constraints Between Schematic and Layout

This video illustrates how to open a constraint comparison report and use it.

18. Liberate AMS Demo

In this video, you will learn how to characterize mixed signal blocks using Liberate AMS and generate a Liberty library (.lib) to enable timing, power, and noise signoff for a full chip including mixed-signal blocks.

19. Using Design Rule Driven Editing

Provides an overview of the various DRD modes.

Rapid Adoption Kits (RAKs)

20. PVS Interactive Short Locator

PVS Interactive Short Locator in PVS 14.1. This is a workshop on the PVS Interactive Short Locator Application. This is designed to help new users learn and use LVS shorts debugging feature more effectively.

21. Virtuoso IPVS

Virtuoso IPVS in IC616 ISR9 / ICADV 12.1 ISR11 / PVS 14.1. Virtuoso IPVS is a mechanism where the PVS verification tool is tightly integrated with the Virtuoso platform. Virtuoso IPVS uses foundry-supplied signoff rules to verify your design.

22. PVS Configurator

PVS Configurator in PVS 14.1. Using configuration files and letting the designers make choices and save them for subsequent runs is an effective way to provide the options to the designer. Using a configuration file also lets the designers choose options directly from the main rule file supplied by the foundry.

Solutions

23. Spectre, SpectreRF, AMS-D, XPS, and APS feature/license matrix for MMSIM 14.1

Explains the number of MMSIM tokens needed for various new analyses and options for Spectre, SpectreRF, AMS-D, XPS, and APS.

24. Need to update license server version for MMSIM 14.1

What to do if MMSIM 14.1 hangs waiting for a license.

25. Distributed processing using SKILL script

IPC commands such as ipcBeginProcess are typically used for generating child processes that execute third-party tools. It is actually also possible to use IPC commands to distribute repetitive SKILL tasks (e.g., flattening of a cell) so as to significantly reduce the total run time.  Includes a detailed example.

26. How to create a via which uses a layer purpose other than drawing

The OpenAccess database does not support layer purposes in case of standardViaDef. Hence it is not possible to have purpose specific standard via. You can use a cdsVia which supports layer purpose. The cdsVia can be defined in the devices section of the technology file or library.

Training Bytes

More short video clips from Cadence Training courses:

• PVS14.1
• Virtuoso Schematic Editor
• Using Virtuoso Constraints Effectively
• Virtuoso Layout Suites Update Training
• Virtuoso Layout Design Basics
• Virtuoso Space-based Router
• SKILL Language Programming Introduction

Training Bytes videos can now be accessed directly from the Resources->Self Learning Library page on http://support.cadence.com.

'Tis the end of an era, folks. It should not be a surprise, but IC 5.1.41 reached End of Support as of 12/31/2014.

1.  Where do I find the support lifecycle dates (e.g., End of Support) for Cadence releases?

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/LifeCycle/EORsupported.html

2.  Where do I find the product lifecycle letters?

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/LifeCycle/EOL_Letters.html

Videos

3. Enter Points for Create and Edit Commands

This video demonstrates how to use the Enter Points form and Status toolbar to specify points for create and edit commands.

4. Analog IP Verification Seminar ADC channel containing eight videos

This video channel walks through a set of eight videos that are designed to accompany the ADE Verification Workshop (available on Rapid Adoption Kit page).

• Data Converter – ADC
• SAR ADC design and verification
• Simulations for SAR ADC, Effective Number of Bits (ENOB)
• Capacitor DAC Measurements
• Clock Generator Measurements
• ADC Transient SINAD Measurement
• ADC Verification Methodology, Best Practices
• In Closing

5.  Analog IP Verification Seminar PLL channel containing six videos

Similarly, this video channel walks through a set of six videos that are designed to accompany the PLL Verification Workshop (available on Rapid Adoption Kit page).

• Phase-Locked Loop
• PLL Overview
• Phase Domain Model
• PLL Block Examples
• Closed-Loop Output Phase Noise
• Verification Methodology: Spectre APS, RF and AMS Designer, Best Practices

 6. Using License UI to Retrieve Diagnostic Information

This video demonstrates the use of license UI to retrieve diagnostic information.

7. Comparing Parasitics and Resolving Electrical Violations

This video shows how to compare parasitics and resolve electrical violations in Virtuoso Layout EAD Browser.

 8. Verifying the Parasitic Information for a Partial Layout

This video demonstrates how the parasitic information can be verified for a partial layout.

 9. Working with Transient Measurement Assistant

This video demonstrates how to use different features of Transient Measurements assistant, create edge markers, change their threshold values, and generate derived plots.

Solutions

10. lefin: Multiple INFO/WARNING messages for property syntax is not supported while trying to import LEF file in virtuoso

The recommended ways to import a 20nm technology into Virtuoso

11. New "info" save options on Outputs->Save All... form in ADE

The Outputs->Save All form in IC6.1.6 ISR10/ICADV12.1 ISR12 has a new section that allows you to specify all the who/what/where fields for Spectre's info analysis. From captap and oppoint to options and netlist, you can interactively set up where to save them and in what format.

12. How to save and plot operating point parameter for Spectre simulator from ADE L/XL?

Check out the new Outputs->To Be Saved->Select OP Parameters feature in IC6.1.6 ISR10/ICADV12.1 ISR12. It lets you interactively select devices from the schematic and then specify which of their operating point parameters to save for plotting after simulation. Previously, the only way to do this was using a text include file.

13. Spectre can now adjust gmin value over a range automatically to resolve convergence issues

A new option in Spectre to allow it to automatically step gmin up to a specified maximum value until convergence is achieved.

Application Notes

1. Voltus-Fi Power Analysis Support and Power Grid View Generation—Voltus-Fi to Voltus Flow

The Voltus-Fi to Voltus flow provides the complete Cadence power integrity solution for full-chip power integrity analysis for all designs, featuring accurate transistor EMIR analysis and high-quality analog IP grid modeling. This application note covers the process of Voltus-Fi flow based on the 28nm process, Power Grid View generation, and on using Voltus-Fi-generated PGVs for Voltus full-chip level SoC power signoff.

2. Annotation Browser—Quick Start Guide

The Annotation Browser assistant enables you to view, locate, and manage the violation markers generated in the current design by different Virtuoso applications. This document helps you get started with the Annotation Browser assistant in the Virtuoso backend flow.

3. Spectre PSPICE Netlist Support

Spectre now enables the user to include PCB components in PSPICE format into a Spectre integrated circuit simulation. The solution is based on the approach of using a regular Spectre simulation including the Spectre simulator control statements, but additionally allowing to include user define subcircuits in PSPICE format.

4. Arrays in VLS XL

An overview of a new way to create arrays using Generate Selected From Source

Rapid Adoption Kits

5. Introduction to AMS Designer Simulation (updated for IC6.1.6 ISR6 and INCISIV 13.2)

This material uses a simple database consisting of an inverter chain to show the setup and use of AMS Designer. Both the GUI-driven flow with ADE L and the text-based command line flow are shown.

6. IC6.1.6 Rapid Analog Prototyping (RAP) Workshop

This is a front-to-back flow that uses the Virtuoso Constraint System to generate the layout of an analog circuit in an automated manner, in order to obtain early feedback on parasitics and device effects on circuit simulation. The basic design goals and requirements are captured through a set of constraints in the schematic, which are implemented in the layout through automatic placement and routing. The resultant LVS clean layout is then extracted, and the circuit re-simulated using the extracted data. The circuit designer can thus identify issues early on and make necessary changes to quickly iterate through the flow, which helps avoid costly changes late in the cycle and enables faster design convergence.

Also provides pointers to Application Notes on "Using the Virtuoso Constraint System for Layout Automation for Rapid Prototyping" and "Circuit Prospecter in Virtuoso (IC6.1.5/6.1.6): An Overview"

7. Understanding CDF for Operating Point & Model Parameter Annotation

The Component Description Format (CDF) describes the parameters and the attributes of parameters of individual components and libraries of components. The CDF lets you create and describe your own components. A CDF description assigns parameters and parameter attributes to libraries and cells for many purposes:

• Assigning parameter names and values
• Allocating units and default values
• Checking that values lie within specified ranges
• Dynamically changing how parameters are displayed depending on predefined conditions
• Executing a SKILL callback function whenever certain information is changed

Videos

8. Training Bytes videos from the Virtuoso Layout Pro course

9. Virtuoso Layout Suite: Label Update feature

Label Update feature allows the designer to quickly and intuitively modify Pin Labels and Text Labels to make them readable and aesthetic, making easier to work on the design.

10. Placing I/O pins generated by Layout XL Generate All From Source command to the location of instance pins

Describes how to place I/O pins generated by LayoutXL's Generate All From Source command to the location of instance pins.

11. Understanding the GDS Merge Flow in XStream

This video shows how multiple GDS files are merged during XStream translation in different scenarios.

Solutions

12. Abstract Generator FinFET support in ICADV12.1 release

How does Abstract Generator handle ANTENNAGATEAREA extraction for FinFETs?

1. Cadence Online Support has a sleek new design along with support for iPAD and Android tablet (7" and above).   Find out what's new. (Note: Some users are experiencing display issues in Chrome version 41 and 42. Cadence is working to find a resolution. If you experience this, we suggest you use IE or Firefox until a fix for Chrome is identified.)

Rapid Adoption Kits

2. Design Rule Driven (DRD) Editing and DRD Compactor (IC6.1.6 ISR9/ICADV12.1 ISR11): DRD is a DRC rule checking tool in Virtuoso. It checks the layout against the design rules defined as constraints in the DFII ASCII technology file. DRD provides both interactive and batch modes of operation. What you will learn:

• DRD Overview
• DRD Operating Modes
• Interactive Display Features
• DRD Constraint Support
• DRD Smart Snap
• DRD Targets
• DRD Compactor
• Compactor Bindkeys

Application Notes

3. Chip-Finishing: Terminology and Things You Should Know: The purpose of this document is to describe various terminologies and concepts related to chip finishing.

4. Recommendations and Tips for the PVS LVS Flow: This document lists the recommendations and tips that can be very helpful during the PVS LVS flow.

5. Virtuoso Analog Design Environment XL: Managing Setup and Results: This "best practices" document describes how to use setup states, work with simulation history, rerun unfinished/error points, perform incremental simulation, and import/export setup in ADE XL.

6. Customizing Create Guard Ring Form: This document explains how the Create Guard Ring form can be customized using specific triggers and SKILL APIs..

Videos

7. Annotation Balloons and Annotating Multiple Corners/Points in ADE XL: This video explains annotation balloons and how to annotate multiple corners/points in ADE XL. Plus, several Training Bytes videos from the Virtuoso Layout Pro training class.

Community

8. CDNLive Silicon Valley 2015 Proceedings—Over 90 Presentations Available: Links to CDNLive presentations and additional articles about the event. 

Solutions

9. How to save OCEAN script using SKILL for a given ADE L state? Example Skill code to start an ADE L session, load an ADE L state, and then save the OCEAN script for that session.

10. Overview on Virtuoso FinFET Support: I am looking for the information on FinFET-based design support in Virtuoso Layout Editing tool. Where can I find the same?

11. How to re-evaluate expressions on previous histories in ADE XL: You are using ADE XL environment using IC616. You would like to add and/or modify some measurements/expressions and evaluate those across one or more previously run histories (without running those simulation runs again). There is a new feature in IC6.1.6 ISR11 which enables you to do this.

12. Subwindows now sortable in ViVA: ViVA has been enhanced in IC 6.1.6 ISR11 and ICADV 12.1 ISR13 with this feature.  You can now drag and drop in the Subwindows assistant and the graph location will change.

13. How to sweep config views in ADE XL: You want to run simulations on the same test and change view to use in HED.  For example, you want to run schematic and av_extracted. This enhancement has been made in IC 616 ISR11 and ICADV 12.1 ISR13.

14. Function names in calculator buffer clickable to populate function panel template for editing: An enhancement has been made in IC 6.1.6 ISR11 and ICADV 12.1 ISR13 to the calculator.  Calculator functions in the buffer are now "clickable".  If you click on highlighted text in the buffer, the function panel will open with the fields filled in. 

15. Does virtuoso has OASIS format  translator for layout exchange like XStream Out and In for GDSII: Yes, the IC6.1.6 is the official release for OASIS translator support.  This solution describes how to use this flow.

Several new FAQ/Shortcut documents have been added or updated:

16. Analog Design Environment L Frequently Asked Questions

17. Virtuoso Visualization and Analysis XL Frequently Asked Questions

18. Virtuoso Schematic Editor: Productivity Shortcuts

19. Virtuoso Fluid Guard Ring Frequently Asked Questions

Application Notes

1. Spectre PSPICE Netlist Support

Spectre technologyenables the user to include PCB components in PSPICE format into a Spectre integrated circuit simulation. The solution is based on the approach of using a regular Spectre simulation including the Spectre simulator control statements, but additionally allowing inclusion of user-defined sub-circuits in PSPICE format.

2. Setting Up Liberate MX for Various Usage Models

This application note is intended to assist you in understanding the purpose and method of Liberate MX and to guide you to choose the usage model that best suits the design that you are characterizing.

3. Liberate MX: Debugging Netlist Issues

When setting up an instance that is to be characterized using Liberate MX, the user needs to provide certain circuit information such as rails and bitcell. If the user does not provide sufficient information about this, the characterization does not run appropriately. In this application note, we will discuss the settings required to characterize an instance and how to determine if the required information is missing.

4. Characterizing Minimum Period and Minimum Pulse Width Using Liberate MX

The characterization of minimum period and minimum pulse width arcs are amongst the most complicated arcs in memory characterization. Each is made up of multiple components that must all be characterized with the maximum value being stored in the library file.

5. Using and Debugging the Liberate MX Validation Flow

The Liberate MX validation flow enables the user to test the numbers in a library file by running a simulation with minimum values for the stimulated arcs. This is commonly called an 'at speed' test. This test allows the user to verify that the memory is functional with the timing numbers in the library file.

Rapid Adoption Kits

6. Basic VCP/VSR Standard Cell Flow

Virtuoso Layout Suite XL and GXL products offer many assisted and automatic capabilities. With the continuous need for higher productivity, and more designs in the custom space, it makes sense to move to a slightly higher level of abstraction, which is referred to as a connectivity-driven design flow. Virtuoso Layout Suite XL is an answer. You can generate the layout based on schematic connectivity and then invoke Virtuoso Custom Placer (VCP) to do the standard cell placement. After placement, the design is ready to be routed.

Videos

7. Virtuoso Layout Suite: Improve Hierarchical Design Editing Performance Using Area Display Feature

8. New Help Menu in Virtuoso

9. Running AMS Simulation in ADE L Using AMS UNL

10. New Training Bytes Videos for Courses:

• Using Virtuoso Constraints Effectively
• Virtuoso Connectivity-Driven Layout Transition

 Solutions

11. How bring the CIW window on top

I am using Virtuoso suite of tools for my design work. I have many design windows open, some may be iconified, some may be buried under other windows. My CIW window gets buried/hidden among these lots of windows. Is there a way to setup a keyboard shortcut so that I can bring the CIW window on the top/front/active whenever I need it?

12. How to redistribute Monte Carlo jobs in ADE XL to better utilize faster machines?

I would like to have the Monte Carlo jobs redistribute during the run. If the MC points assigned to Job on one of the machines in my queue finishes early, then the Job should not remain idle but it should take the MC points from other Job running on different machine.

13. Cannot generate the netlist because instance I0 with place master lib/cell/symbol and another instance with place master lib/cell/symbol1 are bound to the same switch master

In IC6.1.6.500.11 and later there is a change of behavior in OSS around how it handles two different place masters that point to same switch master.

14. How to see the amount of disk space used by a History item in ADE XL

You have many History items.  You want to see how much disk space is being used by a History item.  Is there a way to do this from ADE XL?

15. How to backannotate modgen dummies into single arrayed or iterated instance instead of multiple instances

Dummies added to the layout can be added as individual devices, automated within a modgen or as a mosaic. We can back-annotate the dummies to the schematic for LVS and VXL binding. With a big device array we can can also have a large number of layout dummies (on the periphery).  Back-annotation typically creates an individual schematic device for each. This can result in a large number of schematic dummies which dominate the actual schematic. Commonly such dummies are all of the same dimensions or parameters and connectivity. As such we could consolidate the dummy devices in the schematic. This is probably best handled by creating an iterated instance.  However, presently it is not supported. Can we create modgen dummies as iterated instance in schematic?

16. How to exclude power pins when netlisting Verilog using NC-Verilog?

I am generating verilog netlist for my schematic design using NC-Verilog for schematic environment. I have power pins on my cellview which I don't want netlisted.  How can I generate verilog netlist exlcuding the power pins?

17. How to create a ruler button on Create toolbar of Virtuoso Layout Editor

I am using Virtuoso Layout Editor to create and edit layout design. I know that I can invoke the Ruler from menu Tools -> Create Ruler or using bindkey k. However, is there is a way to add a ruler button on the Create toolbar of Virtuoso Layout Editor. The same toolbar which has Create Instance etc.

18. SKILL  to convert all the top level shapes and vias in a layout to blockage

I have a partially routed layout design. I want to have routing layer blockage or obstruction created on all the top level shapes and vias. In general I want to delete the original shape and just keep the blockages or obstructions because I will keep it as a physical view which can be loaded in a layout later on. However, in some cases I may need the original shapes and vias as well.

19. SKILL script to print a list of unique cells used in a schematic or layout design hierarchy

I use Virtuoso Layout Editor and Virtuoso Schematic Editor to edit my layout and schematic designs. I know that Edit -> Hierarchy -> Print Tree functionality of Virtuoso gives a hierarchical tree of schematic and layout both indicating what all masters have been used at different level of  cellview hierarchy. The tree typically provides the cellview masters which are unique only for one level of design. In other words, if a nmos1v is used at different levels of hierarchy then it gets listed at all levels of hierarchy and is correct. I want a list of unique masters for entire hierarchy rather than one level of design.

Stacy Whiteman