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SKILL for the Skilled: Visiting All Permutations

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In this posting I want to look at several ways of generating permutations of a list. The problem comes up occasionally in fault analysis as well as a few other applications.

Don't generate the list

It is usually a bad idea to try to generate a list of all permutations as the length of that list can be very large for some lists. E.g., a list of the permutations of a list of length ten will be 10! = 3,628,800. What is generally a better idea is to iterate over the permutations one at a time without ever generating them all into a list. This is sometimes referred to as Visiting the permutations with a visitor function.

Even without accumulating a list of permutations, assuming 1 microsecond per iteration, iterating over the permutations of a list of 24 elements will take longer than the age of the universe. This is assuming the universe is 15 billion years old, which is between 23! and 24! microseconds old. Please someone correct me in the comments below if my off the cuff calculation is wrong.

In this blog we present ways to implement the function map_permutations which can be called as follows: (map_permutations VISITOR DATA), where VISITOR is a unary function which will be called on each permutation, and DATA is a list of items.

Brute force approach

The following implementation of map_permutations_BF is more or less a recursive function which implements N consecutive foreach loops, where N is the length of the given list. Each step, 0<=k<=N, of the recursion makes N-k calls to, the local function next. Thus, next reaches the k=N level N! times which it has each time accumulated one permutation.
(defun map_permutations_BF (visit data "ul")
  (let ((N (length data)))
    (labels ((next (so_far k)
               (cond
                 ((eqv k N)
                  (visit (mapcar car so_far)))
                 (t
                  k++
                  (foreach map items data
                    (unless (memq items so_far)
                      (next (cons items so_far) k)))))))
      (next nil 0))))

The example above is SKILL++ code so as always with SKILL++, you need to save it in a file with a .ils extension, or wrap it in (inScheme ...) if pasting into the CIW window.

Example: printing the permutations

Here is a few of examples of how to use map_permutations_BF. The first example prints each permutation of (1 2 3 4) to standard output.
(map_permutations_BF println'(1 2 3 4 5))
Here is the standard out of evaluating that expression:
(4 3 2 1)
(3 4 2 1)
(4 2 3 1)
(2 4 3 1)
(3 2 4 1)
(2 3 4 1)
(4 3 1 2)
(3 4 1 2)
(4 1 3 2)
(1 4 3 2)
(3 1 4 2)
(1 3 4 2)
(4 2 1 3)
(2 4 1 3)
(4 1 2 3)
(1 4 2 3)
(2 1 4 3)
(1 2 4 3)
(3 2 1 4)
(2 3 1 4)
(3 1 2 4)
(1 3 2 4)
(2 1 3 4)
(1 2 3 4)

Counting the permutations

The second example counts the number of permutations of (1 2 3 4 5 6 7 8 9):
(let ((c 0))
  (map_permutations_BF (lambda (_) c++)'(1 2 3 4 5 6 7 8 9))
  c)==> 362880

Collecting a list of permutations

The third example collects and returns the list of permutations of (1 2 3):
(let (data)
  (map_permutations_BF (lambda (p) (push p data))'(1 2 3))
  data)==> ((1 2 3) (2 1 3) (1 3 2) (3 1 2) (2 3 1) (3 2 1))

Trying different algorithms

A very good reference source for discussions and implementations of algorithms in general is Donald Knuth's bookArt of Computer Programming. In particular Volume 4 Fascicle 2 discusses how to generate permutations. The following are three different algorithms implemented from that fascicle.

PLEASE NOTE that I have not tried to improve the readability of the algorithms, but rather I've tried to keep the SKILL code as close as possible to Knuths pseudo-code from the book. I would advise against trying to improve the code. One great advantage of keeping the code as it is, is that you know it works. Another argument for keeping it as it is, and resist improving is that if someone later comes along and reads your code, they can read the referenced pages of Art of Computer Programming to discover the justifications for the implementation as well as discussion of limitations and performance.

Quick review of SKILL prog/go

As with most of the algorithms in Art of Computer Programming, these algorithms are highly optimized and depend on GOTO. The GOTO operator in SKILL is called go and is only available inside (prog ...) within traditional SKILL. Unfortunately, prog/go is NOT available in SKILL++. This means unless you want to convert all the GOTOs in Knuth's code to some other style, you'll have to use .il as your file name suffix when implementing these functions, or of course you may wrap the code in (inSkill ...).

A moral of this story is that sometimes SKILL++ is good for solving a problem, and sometimes traditional SKILL is better. In the SKILL language you have both together. You can use the dialect which works best for your problem space, or you can mix and match as necessary as your application demands.

The SKILL prog allows its body to call return with an argument which causes the prog for to exit and to return the argument which was given to return. For example:

(prog ()
  (return 42)
  (println 'hello))==> 42
In the previous example, the (prog ...) form returns 42, and the line (println 'hello) is never reached. If while executing the body of the (prog ...) form, no (return ...) is encountered, the (prog ...) form returns nil.

Another Knuth-friendly feature of SKILL prog but not the SKILL++ prog is that it allows top-level labels which are valid unquoted operands for the go operator. In the following example, L0, L1, L2, and L3 are labels. Some of these are used by (go ..); in particular (go L1), (go L2), and (go L0).

(prog (n)
  (go L1)

  L0
  (printf "finished\n")
  (return 'done)

  L1
  n = 0

  L2
  (printf "n=")
  (println n)

  L3
  (if (n < 12)
      then n++
           (go L2)
      else (go L0))

  (printf 'never_reached))
You'll find this prog/go construct useful when transcribing Knuth's algorithms.

Plain changes

The following implements algorithm P (Plain changes) from Donald E. Knuth, The Art of Computer Programming Volume 4 Fascicle 2, Generating All Tuples and Permutations, page 42.
(defun map_permutations_P (visit data "ul")
  (letseq ((n (length data))
           (a (listToVector (cons nil data)))
           (c (makeVector (add1 n)))
           (o (makeVector (add1 n)))
           j
           s
           q)
   (prog ()
     P1 ; Initialize
     (for j 1 n
       c[j] = 0
       o[j] = 1)
     P2 ; Visit
     (funcall visit (cdr (vectorToList a)))
     P3 ; Prepare for change.
     j = n
     s = 0
     P4 ; Ready to change?
     q = c[j] + o[j]
     (cond
       ((q < 0)
        (go P7))
       ((q == j)
        (go P6)))
     P5 ; Change
     (let ((u j-c[j]+s)
           (v j-q+s));; swap a[v] with a[u]
       a[v] = (prog1 a[u]
                     a[u] = a[v]))
     c[j] = q
     (go P2)

     P6 ; Increase s
     (if (j == 1)
         (return)
         (s++))
     P7 ; Switch direction
     o[j] = -o[j]
     j--
     (go P4))))

Converting Knuth algorithms to SKILL

List vs Array In SKILL you normally work with lists, and consequently you might want to visit the permutations of a list. The Knuth algorithms in this article visits the permutation of a fixed size array. Because of this, these implementations of map_permutations expect lists as input and output, while internally use arrays in-keeping with the Knuth algorithm. Converting between list and array is done using listToVector and vectorToList.

 

Zero indexed vs. one indexed SKILL only provided zero-based arrays. Some of the Knuth algorithms use one-based and some used zero-based arrays. Where appropriate, filler elements are used for the 0th element when the Knuth array is one-based. You'll see expressions such as (funcall visit (cdr (vectorToList a))) in the SKILL implementations, which means the corresponding array is one-based in the Knuth algorithm, so we have to discard the 0th element when passing the data to the visit function. The following table summarizes how to use makeVector, vectorToList, and listToVector with zero-indexed and one-indexed arrays.

 


allocatearray to listlist to array
N element
zero-indexed
(makeVector N)(vectorToList myarr)(listToVector mylist)
N element
one-indexed
(makeVector N+1)(cdr (vectorToList myarr))(listToVector (cons nil mylist))

 

Use of prog/go/return As described above the use of labels and GOTO in the Knuth algorithms is easily implemented using the SKILL (prog ...) construct.

 

Use of do/until Some Knuth algorithms use do/until, which is available in SKILL++ but not in SKILL. We solve this problem by using the following do_until macro, which takes a test expression as first argument, and a body of expressions. The effect is that the body of expressions is evaluated once, and thereafter it is evaluated again and again as long as re-evaluating the tests returns nil.
(defmacro do_until (test @rest body)
  `(progn ,@body
          (while (not ,test)
            ,@body)))

 

Swapping elements Swapping two elements, A and B, can be done as followings, but when this is done an appropriate comment is added.
A = (prog1 B
           B = A)

Ehrlich swaps

The following implements algorithm E (Ehrlich swaps) from Donald E. Knuth, The Art of Computer Programming Volume 4 Fascicle 2, Generating All Tuples and Permutations, page 57. According to Gideon Ehrlich, the original author of this algorithm, the most amazing thing about it is that it works.
(defun map_permutations_E (visit data "ul")
  (letseq ((a (listToVector data))
           (n (length data))
           (b (makeVector n))
           (c (makeVector n+1))
           k
           j)
   (prog ()
     E1 ; Initialize
     (for j 0 n-1
       b[j] = j
       c[j+1] = 0)
     E2 ; Visit
     (funcall visit (vectorToList a))
     E3 ; Find k
     k = 1
     (when (c[k] == k)
       (do_until (c[k] < k)
         c[k] = 0
         k++))
     (if (k == n)
         (return)
         c[k] = c[k] + 1)
     E4 ; Swap
     a[0] = (prog1 a[b[k]]
                   a[b[k]] = a[0])
     E5 ; Flip
     j = 1
     k--
     (while (j < k);; swap b[j] and b[k]
       b[j] = (prog1 b[k]
                     b[k] = b[j])
       j++
       k--)
     (go E2))))

Permutation generation by cyclic shifts

The following implements algorithm C (Permutation generation by cyclic shifts) from Donald E. Knuth, The Art of Computer Programming Volume 4 Fascicle 2, Generating All Tuples and Permutations, page 56.
(defun map_permutations_C (visit data "ul")
  (letseq ((x (listToVector (cons nil data)))
           (n (length data))
           a
           k
           j)
    (prog ()
     C1 ; Initialize
     a = (listToVector (cons nil data))
     C2 ; Visit
     (funcall visit (cdr (vectorToList a)))
     k = n

     C3 ; Shift;; (a1 a2 a3 ..ak) <-- (a2 a3 ...ak a1)
     a[k] = (prog1 a[1]
                   (for j 1 k-1 
                        a[j] = a[j+1]))
     (when (a[k] != x[k])
       (go C2))
     C4 ; Decrease k.
     k--
     (when (k > 1)
       (go C3)))))

Summary

In this article we looked at several things.
  • Four functions for visiting all permutations of a given list. Feel free to copy and paste these implementations into your SKILL programs, but please remember to give credit to Donald Knuth where appropriate.
    • map_permutations_BF -- Brute force
    • map_permutations_C -- Cyclic shifts
    • map_permutations_P -- Plain changes
    • map_permutations_E -- Ehrlich swaps
  • Translating algorithms from Donald Knuth's Art of Computer Programming to SKILL
  • Seldom used features of SKILL (prog ...) such as (go ...)
  • Examples using makeVector, listToVector, and vectorToList.

See Also


Virtuosity: 15 Things I Learned in August by Browsing Cadence Online Support

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Our folks over in Physical Design have been busy churning out helpful Rapid Adoption Kits to demystify lots of useful features in the Virtuoso Layout Suite.  It's a great opportunity to learn some new productivity-boosting tricks.

Application Notes

1. Virtuoso Spectre Transient Noise Analysis

This document discusses the theoretical background of Spectre's transient noise analysis, its implementation and implications, and the latest use model together with many useful time-saving and circuit diagnostic features.  It also provides several detailed tutorial examples.

Rapid Adoption Kits

2. IC 6.1.6 Rapid Analog Prototyping (RAP) Workshop

This is a front-to-back flow that uses the Virtuoso Constraint System to generate the layout of an analog circuit in an automated manner, in order to obtain early feedback on parasitics and device effects on circuit simulation.  Includes an overview presentation, documented tutorial and database.

3. Virtuoso Parameterized Layout Generators (VPLGen)

VPLGen is a new feature that lets you easily generate and reuse layouts for schematic instances which differ by inherited parameter values so that the layouts can be used repeatedly throughout the hierarchy and reused across design libraries. VPLGen is a Cadence-supported hierarchical pcell that does not require coding.  This RAK includes a documented tutorial and database, as well as a video demonstration.

4. VXL Back Annotation

This workshop walks you through an example of how to create a dummy using VXL and then how to back-annotate it into a schematic.  It includes a documented tutorial and database.

5. Update Binding

This workshop is an example of how to take a layout that was created in a non-connectivity environment and make it VXL compliant. It walks through how using the new Update Binding command to simplify the task. Includes a documented tutorial and database.

6. Introduction to Connectivity-Driven Design in VLS XL

The move from Layout L to Layout XL is becoming increasingly important.  The Layout XL environment contains functionality for the implementation of advanced-node designs, such as wire editing, connectivity- and constraint-driven layouts, mosaics, modgens, and electrically aware design. This Rapid Adoption Kit (RAK) will introduce how productivity can be increased by moving from Virtuoso Layout Suite L to Virtuoso Layout Suite XL.  It includes a documented tutorial and database.

7. QuickView Introduction

QuickView is the Cadence stand-alone data viewing tool. It allows you to draw, examine, compare and validate integrated circuit (IC) data in various layout and pattern data formats. Includes documented tutorial and database.

8. IC6.1.6 Pin to Trunk Device-Level Routing

This material steps through the Pin to Trunk Device-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at device-level interconnects. This flow enables users to quickly connect device pins in a structured topology. Includes documented tutorial and database.

9. IC6.1.6 Pin to Trunk Block-Level Routing

This material steps through the Pin to Trunk Block-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at block-level interconnects. This flow enables users to quickly connect block pins in a structured topology. Includes documented tutorial and database.

10. Stamping Conflict Debugging in LVSDE

Resolving stamping conflicts has remained an area of challenge for the designers. The Stamping Conflict Debugger is aimed at easing this process. This RAK is a workshop on the Stamping Conflict Debugger to help new users learn and use this feature more effectively.  Includes documented tutorial and database.

11. PVS Interactive Short Locator

This is a workshop on the PVS Interactive Short Locator Application. You will learn how to find shorts using the Interactive Short Locator, confirm the cause of the short without modifying the layout, add additional labels to help narrow down the shorted paths, resolve multiple labels shorts, and resolve shorts between unlabeled nets. Includes documented tutorial and database.

Solutions

12. How to get the list of output signals and expressions set in ADE L and ADE XL session using SKILL?

Skill code for both ADE L and ADE XL to obtain the saved output signals and expressions.

13. How to create a device check expression for model or primitive

The device check UI can be confusing.  This solution gives step-by-step instructions on how to set up a device checking expression for all devices which use a specific model or subcircuit.

14. How to read/load design variable from a text file to ADE window?

Skill code to read design variable name/value pairs and load the setup into ADE.

15. SKILL Example of OSM Object Sensitive Menu

Object or context-sensitive menus can be very handy.  Here's an example of how to define your own.

 

SKILL for the Skilled: How to Shuffle a List

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The previous post of SKILL for the Skilled presented some ways to systematically visit all permutations of a list. As noted, the time to iterate through all permutations of a large list is prohibitive. If the goal is to find a permutation that meets some criteria then it may work perfectly well to simply test the criteria on randomly chosen permutations of the list and continue doing so until some time-out is reached. Choosing a permutation at random is also called shuffling.

In this article, I want to look at some ways to shuffle a list. In doing so, we'll also see how random numbers work in SKILL and a few examples of how to use them.

Very easy but not very random

An advantage of the implementation of shuffle_a below is that it very easy to remember and easy to implement. An important disadvantage is that it does a poor job of shuffling the given list. It basically asks the SKILL built-in sort to do the work and provides a compare function for sort to use, which provides some randomness. The SKILL expression (random 2) returns either 0 or 1 selected at random. Consequently the expression (onep (random 2)) returns either t or nil chosen at random.
(defun shuffle_a (data)
  (sort (copy data)
        (lambda (_a _b)
          (onep (random 2)))))
For example, (shuffle_a '(1 2)) returns either (1 2) or (2 1), each with 50% likelihood. However (shuffle_a '(1 2 3)) returns one of the following two permutations half of the time (3 1 2), (3 2 1), and one of the other four permutations the other half of the time. Thus, not all permutations are equally likely.

Similarly, there are 24 permutations of (1 2 3 4), but (shuffle_a '(1 2 3 4)) returns one of the following eight permutations half of the time: (1 2 3 4), (1 2 4 3), (2 1 3 4), (2 1 4 3), (3 4 1 2), (3 4 2 1), (4 3 1 2), or (4 3 2 1). And it returns one of the other 16 permutations the other half of the time.

If you need a quick and dirty shuffle algorithm, shuffle_a is decent and easy to remember. But if you need a good shuffle algorithm, use a different one.

Shuffle by partitioning

The following recursive algorithm can be used to shuffle a list of elements. It works similar to a quick sort, but rather than collecting the large and small elements into two respective lists recursively, it randomly partitions some elements into one sub-list and others into another sub-list, then proceeds to apply the same algorithm recursively onto those two sub-lists.
(defun shuffle_b (data)
  (cond
    ((cddr data) ; more than 2 elements?
     (let (left right)
       (foreach item data
         (if (zerop (random 2))
             (push item left)
             (push item right)))
       (nconc (shuffle_b left)
              (shuffle_b right))))
    ((zerop (random 2))
     (reverse data))
    (t
     (copy data))))

Shuffle by random selection

The following algorithm shuffle_c, works by continuing to randomly choose element at random from the list, push that element onto a new list, and remove it from the old list, continuing until a single element remains, then finally pushing it onto the list.

The expression r = (random n) returns a number 0 <= r < n

(defun shuffle_c (data)
  (let ((n (length data))
        r
        p
        shuffled)
    (while (cdr data);; choose a random element: data[r]
      r = (random n) ; randomly choose 0 <= r < n
      p = (nthcdr r data);; add data[r] to shuffled
      (push (car p)
            shuffled);; remove data[r] from data
      data = (nconc (ldiff data p)
                    (cdr p));; decrement n
      n--)
    (when data
      (push (car data) shuffled))
    shuffled))

How do you remove an element from a list?

There is a subtle trick in the code for shuffle_c: how to remove an element from a list. The built-in SKILL function remove won't exactly do the trick. Actually, remove works fine if the elements of the list are unique, but not if the list has duplicate elements. The SKILL remove function actually removes all elements from the given list which are equal to the given element. For example (remove 42 '(0 42 1 42 2 42 3)) will return (1 2 3), whereas we want a function, remove_once which works as: (remove_once 42 '(0 42 1 42 2 42 3)) ==> (0 1 42 2 42 3).

You might implement remove_once as follows:

(defun remove_once (data item)
  (let ((p (member item data)))
    (nconc (ldiff data p)
           (cdr p))))
What the shuffle_c function does is chooses an element of the list by position, and then removes the element in that position. For example, given the list mylist=(42 1 42 2 42 3), if we choose the element in position 2 (0-based index), which is the second 42 in the list, we can divide the list in two halves, right and left. The right portion is obtained by calling (nthcdr 2 mylist) ==> (42 2 42 3). The left portion is obtained by left=(ldiff mylist right)==>(42 1). Given right and left, we can produce a new list equal to the original list but with the element at position 2 removed by appending the two lists left and (cdr right).

How do you select an element at random?

Given a list of elements, the following function will select an element at random from it.
(defun random_element (data)
  (when data
    (nth (random (length data)) data)))
Be careful with this function: if given an empty list, (random 0) triggers an error.

Shorter version of shuffle

The following implementation of shuffle_d is more or less the same algorithm as shuffle_c but uses the helper functions random_element and remove_once.
(defun shuffle_d (data)
  (let (shuffled
        e)
    (while data
      e = (random_element data)
      (push e shuffled)
      data = (remove_once data e))
    shuffled))

Challenge to the reader

If you know another clever way to shuffle a list, please post the code to the comment section of this article below.

Summary

In this article four versions of the shuffle function were presented.
  • shuffle_a: a very short implementation of an inferior sorting algorithm
  • shuffle_b: a recursive divide and conquer shuffle algorithm
  • shuffle_c: an imperative, iterative algorithm for shuffling
  • shuffle_d: similar to shuffle_c but easier because it makes use of helper functions

In addition we looked at two other functions:

  • remove_once: an efficient algorithm for removing a maximum of one element from a list
  • random_element: return a randomly selected element from a list

Virtuosity: 16 Things I Learned in September by Browsing Cadence Online Support

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Rapid Adoption Kits

By now, I think you know what RAKs are, and that they include a detailed instructional document and database.  Use the title link above to access the main landing page and browse all the available material.

1. DRD-based Interactive Compactor

The DRD-based interactive compactor can help you change the spacing between existing objects in your layout either through compaction or spreading. It can also fix spacing violations between shapes in your layout.

2. FastXOR

PVS XOR is a widely and highly needed application by designers to compare their layout databases.

3. IC 6.1.6 Crosstalk

This kit outlines a strategy for crosstalk prevention during both interactive and automated routing, using Virtuoso constraints.

4. PVS Interactive Short Locator

This is a workshop on the PVS Interactive Short Locator Application. This is designed to help new users learn and use the LVS shorts debugging feature more effectively.

5. Stamping Conflict Debugging in LVSDE

Resolving Stamping Conflicts has remained an area of challenge for the designers and the Stamping Conflict Debugger has been aimed at easing this process. This RAK is a workshop on the Stamping Conflict Debugger to help new users learn and use this feature more effectively.

6. IC 6.1.6 Pin to Trunk Block-Level Routing

This material steps through the Pin to Trunk Block-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at block-level interconnects. This flow enables users to quickly connect block pins in a structured topology.

7. IC 6.1.6 Pin to Trunk Device-Level Routing

This material steps through the Pin to Trunk Device-Level Routing Flow in Virtuoso in IC 6.1.6. The objective of this flow is to increase layout productivity through improved routing functionality aimed at device-level interconnect. This flow enables users to quickly connect device pins in a structured topology.

Videos

8. Using amsDmv To Complement ADE XL Spec Comparision Form

This video highlights several very useful, but under-utilized aspects of the Custom IC tool suite--using ADE XL Spec Comparison to compare measured results, using amsDMV to compare waveforms and using amsDmv as a simulation cockpit to analyze small design changes.

9. Physical Verification System: Debugging DRC Results

This video is intended for new PVS users to help them quickly understand how to analyze and debug the PVS DRC run results using the DRC Debug Environment.

Application Notes

10. PVS Bindings by Name during PVS LVS Run

This document talks about the default PVS behavior around binding cells and pins across layout and schematic as well as discusses various commands to control the binding behavior, mostly using a question and answer style.

11. Circuit Prospector in Virtuoso (IC 6.1.5/6.1.6): An Overview

The Circuit Prospector is another under-utilized Virtuoso feature which can help identify structures and objects in a schematic with important electrical or topological characteristics.  This document provides a guide to setup, usage an customization of this Assistant.

Solutions

12. FAQ: Tips for Using S-Parameters in Spectre and SpectreRF

A great collection of tips and articles on using s-parameters in Spectre and SpectreRF.  Also, check out Tawna's library of useful blog articles in the RF space.

13. SKILL examples of forms, fields and menus

Everything you always wanted to know about creating forms and menus in SKILL, with example database and code.

14. Is there a way to run Mark Net in a user defined area of the design?

Why, yes.  Yes there is.

15. Virtuoso Layout Editor: Change color of the ruler - New Environment Variable

16. Pin Placer verses (sic) Pin Optimizer, which one to use and when?

This solution explains the difference between the 2 pin placement engines in VLS XL and provides guidelines for which one to use and when.

 

Stacy Whiteman 

Virtuosity: 12 Things I Learned in October by Browsing Cadence Online Support

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Lots of routing, a little AMS, and finishing off with some fun...

Application Notes

1. Constraint Implementation and Validation in interoperability flow

The Mixed Signal Interoperability (MSI) flow allows designers to seamlessly transfer and implement routing constraints from analog to digital designs.  This document covers the steps required to apply and implement routing constraints in Encounter and validate these constraints using the Physical Verification System-Constraint Validation (PVS-CV) utility.

Rapid Adoption Kits

All RAKs include a detailed instructional document and database.

2. Virtuoso Interconnect Routing using VSR

Describes a new use model for running VSR using the Wire Assistant and top-level signal net routing in an analog top-level design.

3. Static and Dynamic Checks

This material describes the usage of the Spectre APS/XPS static and dynamic design checks. These checks may be used to identify typical design problems including high impedance nodes, DC leakage paths, extreme rise and fall times, excessive device currents, setup and hold timing errors, voltage domain issues, or connectivity problems. While the static checks are basic topology checks, the dynamic checks are performed during a Spectre APS/XPS transient simulation.

4. Mixed-Signal Verification -- System Verilog Real Number Modeling

Introduces the new SV-RNM 1800-2012 LRM capabilities that have been made available to aid in mixed-signal verification flows. It provides a basis for the production-level solution that we currently have in Incisive 12.2/ 13.1 that are SV-RNM 1800-2009 LRM centric. Then the RAK introduces the newer capabilities made available by the SV-RNM 1800-2012 LRM that enhance the SV-RNM modeling performance and functionality. The designer will be able to explore the user-defined types and resolution functions along with the debug capabilities made available by SimVision for these new features. Also includes an overview video.

5. Parasitic-Aware Design Using Custom Cells

ADE GXL Parasitic-Aware Design (PAD) features are used to investigate the effect of parasitic devices on a circuit.  RAK has been designed to highlight the features and functionality of the PAD flow in the IC 6.1.6 release, which enable the user to incorporate parasitic estimates into their simulations using custom parasitic elements.  Also includes an appendix on how to build a custom parasitic cell.  This RAK pairs well with the earlier Parasitic-Aware Design Workshop, which covers the entire PAD flow, including parasitic estimation, filtering extracted parasitics, parasitic stitching from extracted views, and parasitic reporting.

Videos

6. AMS Simulation with Multiple Logic Disciplines and Power Supplies on a Single Instance

Demonstrates how to run an AMS simulation with an instance that has multiple logic disciplines and power supplies. In this particular example, the instance has both 1.2V and 3.3V ports.

7. IC 6.1.6 Pin to Trunk Block-Level Routing

Frequent browsers of the Cadence Online Support Video Library may have noticed that many video demonstrations have been organized into "channels" or playlists.  Perfect for binge-watching on a rainy afternoon.  This channel features two videos covering block-level pin-to-trunk routing basics and routing between blocks.

8. IC 6.1.6 Pin To Trunk Device-Level Routing

These three videos cover device-level pin-to-trunk routing basics, wire assistant overrides, routing scope, and via control.

Cadence Community Blogs

9. IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)

Nice FAQ-style overview of the new features in the Virtuoso Space-Based Router in the context of chip/block assembly routing in mixed-signal analog-on-top (AoT) designs.

10. Spectre XPS -- Cadence Reinvents FastSPICE Simulation

Although it has been under evaluation at several Early Access Partner customers for some months, the official launch of the Spectre XPS FastSPICE simulator was announced in October.  Initially targeted at SRAM characterization, in conjuction with Cadence's Liberate MX tool, Spectre XPS uses advanced partitioning techniques to achieve tremendous performance gains.  

11. EDA Consortium Extravaganza Celebrates 50 Years of Design Automation

"Engineering" and "Extravaganza" are not two words normally seen together, so you've got to gawk a bit when the geeks come out to play.  The 50-year anniversary, and the event, even made it into the Huffington Post, where, no doubt, my mother is still scratching her head wondering "what exactly is it that you do"? 

12. Unhinged

Our new Editor-in-Chief just released Episode 4 of this dynamic, off-the-wall Web show which combines geeky humor with actual news and interesting interviews in a format well-suited to short-attention-span creatures such as myself.  You may laugh, you may cringe, but you will be entertained. 

 

 

 

 

SKILL for the Skilled: Simple Testing Macros

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In this post I want to look at an easy way to write simple self-testing code. This includes using the SKILL built-in assert macro and a few other macros which you can derive from it.

The assert macro

This new macro, assert, was added to SKILL in SKILL version 32. You can find out which version of SKILL you are using with the SKILL functiongetSkillVersion, which returns a string such as"SKILL32.00" or "SKILL33.00".

Using this macro is simple. In its simplest form, you wrap any single expression within (assert ...). At evaluation time this will trigger an error if the expression evaluates to nil.

CIW> (assert 1 + 1 == 2)nil

CIW> (assert 2 + 2 == 5)*Error* ASSERT FAILED: ((2 + 2) == 5)<<< Stack Trace >>>
error("ASSERT FAILED: %L\n" '((2 + 2) == 5))
unless(((2 + 2) == 5) error("ASSERT FAILED: %L\n" '(& == 5)))

You can also specify the error message using printf-style arguments.

CIW> (defun testit (x "n")
       (assert x > 3 "expecting x > 3, not %L" x)
       x-3)

CIW> (testit 12)9

CIW> (testit 2)*Error* expecting x > 3, not 2<<< Stack Trace >>>
error("expecting x > 3, not %L" x)
unless((x > 3) error("expecting x > 3, not %L" x))
testit(2)

What is a macro?

Macros are a feature in many lisps including emacs lisp, common lisp, and SKILL. Consequently, you can find tons of information on the Internet explaining lisp macros. A quick Google search for "lisp macro" returns pages of useful results.

In particular, a SKILL macro is a special type of function which computes and returns another piece of SKILL code in the form of an s-expression. This capability allows SKILL programs to write SKILL programs as a function of their raw, unevaluated, operands at the call-site. Although macros can certainly be abused, when used correctly SKILL macros can greatly enhance readability by abstracting away certain details, or by automating repetitive patterns.

You can find out more about SKILL macros by consulting the Cadence documentation. There is also an Advanced SKILL Programming class which Cadence Educational Services offers.

In-line tests

You can use assert inside your functions for run-time checks. You can also use assert at the top level of your SKILL files for load-time checks. This has an added advantage of helping the person who reads your code to understand how the function you are defining is used. In the following example anyone who reads your function definition can immediately see some examples of how to use the function.
;; Sort a list of strings case independently into alphabetical order.
(defun sort_case_independent (words "l")
  (sort words (lambda (w1 w2)
                (alphalessp (lowerCase w1)
                            (lowerCase w2)))))

(assert nil 
        ; works for empty list?
        == (sort_case_independent nil)) 

(assert '("a"); works for singleton list?
         ==  (sort_case_independent '("a")))) 

(assert '("a" "B")
         == (sort_case_independent '("B" "a")))

(assert '("a" "B")
         == (sort_case_independent '("a" "B")))

(assert '("A" "b")
        == (sort_case_independent '("b" "A")))

(assert '("A" "b")
        == (sort_case_independent '("A" "b")))

(assert '("A" "b" "c" "D")
        == (sort_case_independent '("c" "D" "A" "b")))
Writing your SKILL files to include these top-level assertions has yet another advantage: if someone later modifies your function, sort_case_independent, the tests will run the next time anyone loads the file. This means if an error has been introduced in the function, some sanity testing happens at load time. Furthermore, if someone enhances the function in a way that breaks backward compatibility, the assertion will fail at load time.

Defining assert if it is missing

If you are using a version of Virtuoso, Allegro, etc, which does not contain a definition of assert, you can define it yourself.
(unless (isCallable 'assert)
  (defmacro assert (expression @rest printf_style_args) 
    (if printf_style_args 
        `(unless ,expression
           (error ,@printf_style_args))
        `(unless ,expression
           (error "ASSERTION FAILED: %L\n" ',expression)))))

The assert_test macro

Some unit testing frameworks supply assertion functions such as assert_less, assert_greater, assert_equal, assert_not_equal. It is possible in SKILL to define a single assertion macro called, assert_test, which provides all these capabilities in one. You don't really need assert_equal, assert_not_equal, asset_lessp etc...

This macro is useful for building test cases. This macro attempts to output a helpful message if the assertion fails. The message includes the parameters to the testing expression, and the values they evaluate to. For example:

CIW> A = 33

CIW> B = 22

CIW> (assert_test A+B == B+2) *Error* (A + B)
  --> 3
(B + 2)
  --> 4
FAILED ASSERTION: ((A + B) == (B + 2))<<< Stack Trace >>>
...
CIW> (assert_test A+B > B+2)
*Error* (A + B)
  --> 3
(B + 2)
  --> 4
FAILED ASSERTION: ((A + B) > (B + 2))<<< Stack Trace >>>
...

The intelligent thing about assert_test as can be seen from the above example, is that it constructs an error message which tells you the text of the assertion that failed: ((A + B) == (B + 2)). It also tells you the arguments to the testing function in both raw and evaluated form: (A + B) --> 3 and (B + 2) --> 4

The macro definition is not trivial, but the code is given here. You don't really need to understand how it works in order to use it.

;; ARGUMENTS:
;;   expr - an expression to evaluate, asserting that it does not return nil
;;   ?ident ident - specifies an optional identifier which will be printed with [%L] in
;;                     the output if the assertion fails.  This will help you identify the
;;                     exact assertion that failed when scanning a testing log file.
;;   printf_style_args - additional printed information which will be output if the
;;                     assertion fails.
(defmacro assert_test (expr @key ident @rest printf_style_args)
  (if (atom expr)
      `(assert ,expr)
      (let ((extra (if printf_style_args
                       `(strcat "\n" (sprintf nil ,@printf_style_args))"")))
        (destructuringBind (operator @rest operands) expr
          (letseq ((vars (foreach mapcar _operand operands
                           (gensym)))
                   (bindings (foreach mapcar (var operand) vars operands
                               (list var operand)))
                   (assertion `(,operator ,@vars))
                   (errors (foreach mapcar (var operand) vars operands
                             `(sprintf nil "%L\n  --> %L" ',operand ,var))))
            `(let ,bindings
               (unless ,assertion
                 (error "%s%s%s"
                        (if ',ident
                            (sprintf nil "[%L] " ,ident)"")
                        (buildString (list ,@errors
                                           (sprintf nil "FAILED ASSERTION: %L" ',expr))"\n")
                        ,extra))))))))

The assert_fails macro

With the assertion macros presented above you can pretty robustly make assertions about the return values of functions. A limitation, however, is you cannot easily make assertions about the corner cases where your function triggers an error.

The following macro,assert_fails, provides the ability to assert that an expression triggers an error. For example, thesort_case_independent function defined above will fail, triggering an error, if given a list containing a non-string.

CIW> (sort_case_independent '("a" "b" 42 "c" "d"))*Error* lowerCase: argument #1 should be either a string or a symbol (type template = "S") at line 112 of file "*ciwInPort*" - 42<<< Stack Trace >>>
lowerCase(w2)
alphalessp(lowerCase(w1) lowerCase(w2))
funobj@0x2cac49a8("a" 42)
sort(words lambda((w1 w2) alphalessp(lowerCase(w1) lowerCase(w2))))
sort_case_independent('("a" "b"))

You could fix this by enhancing the function to do something reasonable in such a situation. Or you could simply document the limitation, in which case you might want to extend the in-line test cases as well.

(assert_fails (sort_case_independent '("a" "b" 42 "c" "d")))

Here is an implementation of such a assert_fails macro.

(defmacro assert_fails (expression)
  `(assert (not (errset ,expression))"EXPECTING FAILURE: %L\n"',expression))

Summary

In this article we looked at the assert macro, which is probably in the version of Virtuoso or Allegro you are using, and if not you can easily define it yourself. We also looked at assert_test and assert_fails which you can define yourself. You can use these three macros to easily improve the robustness of your SKILL programs.

See Also

SKILL for the Skilled: SKILL++ hi App Forms

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One way to learn how to use the SKILL++ Object System is by extending an application which already exists. Once you understand how extension by inheritance works, it will be easier to implement SKILL++ applications from the ground up. I.e., if you understand inheritance, you can better architect your application to prepare for it.

This episode of SKILL for the Skilled starts with an existing SKILL++ GUI application and extends it several times. This is done each time by declaring a subclass of an existing SKILL++ class and adding methods on existing generic functions.

Overview

The application presented here is a hi GUI which walks an instance of a designated SKILL++ class across a designated design hierarchy. If the class of the instance is the base class smpDescendDesign, each cellView in the hierarchy is silently visited and, thus, is opened into virtual memory.

Please download theSKILL++ code, load the file smpGUI.ils, and call the function smpGUI().

The SKILL++ programmer is allowed to extend this base class to augment, circumvent, or modify some of its behavior.

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In the following paragraphs we'll extend this application in several ways:

  • Add diagnostic messages for each cellView visited
  • Save the modified cellViews encountered
  • Accommodate descent of schematics
  • Descend schematic with diagnostic messages

The Sample GUI

What does this application do? If you trace the smpWalk function and press Apply on the form, you get an idea of what's happening.

 

|[4]smpWalk(#{smpDescendDesign} db:0x311f7d9a)
|[4]smpWalk (smpDescendDesign t)(#{smpDescendDesign} db:0x311f7d9a)
|[6]smpWalk(#{smpDescendDesign 0x2ef12410} db:0x311f7a9a ?depth 1 ?lineage ... )
|[6]smpWalk (smpDescendDesign t)(#{smpDescendDesign} db:0x311f7a9a ?depth 1 ?lineage ... )
|[6]smpWalk (smpDescendDesign t) --> nil
|[6]smpWalk --> nil

...[stuff omitted]...

|[4]smpWalk (smpDescendDesign t) --> (db:0x311f7bf3 db:0x311f7bf2 db:0x311f7b23 db:0x311f7b22 db:0x311f7b1d ... )
|[4]smpWalk --> (db:0x311f7bf3 db:0x311f7bf2 db:0x311f7b23 db:0x311f7b22 db:0x311f7b1d ... )

The SKILL++ code is given insmpGUI.ils and smpDescendDesign.ils. You can experiment with it by loading startup.ils and calling the function smpGUI().

Extending the Application

A well-written SKILL++ application is extended not by modifying the original source code, but rather by creating sub-classes of built-in classes and providing methods on generic functions. This sample application defines as extensibility points a class named smpDescendDesign and several generic functions, smpDescription, smpWalk,smpGetSwitchMaster, and smpFilterInstances.

If a SKILL++ application is documented well enough, you will be able to read the documentation to understand which classes can be extended and which methods need to be overwritten to accomplish the desired results. Lacking sufficient documentation, you can read the source code comments.

Printing the Design Hierarchy

We want to extend the application so that the Class Name field of the GUI contains both strings: smpDescendDesign and smpPrintDesign. When the user selects smpPrintDesign and presses OK/Apply, an additional thing should happen: in particular, as the hierarchy is being visited, messages should be printed to standard output, indicating information about the cellViews visited, such as the following:
 0 -> ether_adc45n adc_sample_hold     layout: 
 1 -->    gpdk045  pmoscap2v     layout: |C3
 1 -->    gpdk045  pmoscap2v     layout: |C4
 1 --> ether_adc45n inv_2x_hv_small     layout: |I58
 2 --->    gpdk045     nmos2v     layout: |I58/|NM0
 2 --->    gpdk045     pmos2v     layout: |I58/|PM0

What is a Class?

Long-time readers may recall a series of SKILL for the Skilled articles some time ago,Introduction to Classes (parts 1 through 5).

A class in SKILL++ is an object which specifies a common structure of other objects (called instances). A class has at least one parent (called a direct super-class), and zero or more children (called direct sub-classes). The set of all classes form a directed acyclic graph from a special class at the top called t downward from super-class to sub-class ending at leaf-level classes at the bottom. The list of the class itself and all such parent classes starting with the class and terminating at t is called the list of super-classes. In SKILL++ this is a well defined and ordered list.

The class hierarchy is important because a class inherits structure and behavior from all its super-classes.

Creating a Subclass

The SKILL built-in macro defclass is used to create a new class or a sub-class of an existing class. If you don't specify an explicit super-class when creating a new class, its parent will be the special built-in class called standardObject.

To create a class named smpPrintDesign inheriting from smpDescendDesign, use the following syntax:

(defclass smpPrintDesign (smpDescendDesign)
   ())

This defines a simple class hierarchy as shown in the graphic:

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As far as SKILL++ is concerned, that's all that is necessary to create a class. However, to register the class with the sample application, the API function smpAddClass is provided. You need to call it with the name of the class. This tells the GUI form creation function to add the string "smpPrintDesign" to the cyclic field choices.

(smpAddClass 'smpPrintDesign)
You are free to create other building-block classes without registering them with smpAddClass. Those building-block classes won't appear in the GUI.

At this point you will have two Class Name choices in the GUI, but pressing OK/Apply will do the same thing regardless of which one is active.

What is a Generic Function?

While classes determine hierarchy and structure, generic functions and their methods implement behavior. A generic function declares the interface for all the methods of the same name. SKILL++ enforces parameter list congruency of all the methods of a generic function. SKILL++ programmers must be careful to enforce return value of the methods in a way which makes sense for the particular application.

For example, the return value of smpDescription must be a string because that string will be used as the value of a multi-line-string field in an application form.

The Sample API

This sample application pre-defines several generic functions which together with the smpDescendDesign class form the API for extending the application. A SKILL++ programmer is allowed to specialize methods of these generic functions on application-specific classes derived from smpDescendDesign.

The generic functions with their documentation are repeated here, but may also be found in the file smpGUI.ils.

 

smpDescription
(defgeneric smpDescription (obj))
Returns a string (with embedded \n characters) describing the action to be preformed if OK/Apply is pressed on the GUI while a particular class name is selected.
Methods on this generic function should return a string, possibly strcat'ing the result with callNextMethod().

smpWalk
(defgeneric smpWalk (obj cv @key lineage (depth 0) @rest _others))
Descend the hierarchy of the given cellview. Methods on this generic function may perform some action for side effect on the given cellView. Primary methods should call callNextMethod if they wish the descent to go deeper, and should avoid calling callNextMethod to prune the descent at this point. The return value of smpWalk is not specified.
ARGUMENTS:obj the object being specializedcv the opened cellView which is being visitedlineage a list of instances representing the lineage of this cellView back to the top level. The first element of lineage is the immediate parent of the cellView and the top-level instance is the last element of lineagedepth an integer indicating the hierarchy level. 0 indicates the top-level cellView.

smpFilterInstances
(defgeneric smpFilterInstances (obj cv))
Given a cellView, return the list of instances whose masters should be descended. The order of the list returned from smpFilterInstances is unimportant.

smpGetSwitchMaster
(defgeneric smpGetSwitchMaster (obj inst))
Given an instance in a cellView being visited by smpWalk,smpGetSwitchMaster returns the cellView to descend into. IfsmpGetSwitchMaster returns nil, then the descent is pruned at this point.

Updating the GUI Description Field

The GUI has a description field. We'd like this description to change as the user selects a different class name. We can do this by implementing the method smpDescription specialized on the new class. If you look at the smpDescription documentation above the comment on the generic function definition, you'll see some instructions for implementing methods.

These instructions describe how to implement a method on smpDescription: all smpDescription methods are unary functions, each method is expected to return a string.

(defmethod smpDescription ((_obj smpPrintDesign))
  (strcat (callNextMethod)"\nAnd print the names of each lib/cell/view encountered."))

Now if you interactively select the Class Name smpPrintDesign in the GUI, the description should change as shown here. As you see, the original text Descend the design hierarchy. has been augmented by the string concatenated by the new method.

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Adding the Diagnostic Messages

We now want to add a method to the smpWalk generic function. For clues on how to do this, consult the smpWalk documentation above. We can see that each method must have two required arguments, and must accept some optional arguments, in particular ?lineage and ?depth.
(defmethod smpWalk ((_obj smpPrintDesign) cv @key lineage (depth 0))
  (printf "%2d " depth)
  (for _i 0 depth (printf "-"))
  (printf "> ")
  (printf "%10s %10s %10s: %s\n"
          cv~>libName cv~>cellName cv~>viewName
          (buildString (reverse lineage~>name) "/"))
  (callNextMethod))

The method smpWalk specializing on smpPrintDesign prints some information about the cellView being visited, then calls callNextMethod, which continues with the descent.

The result of pressing the OK/Apply button is now something like the following being printed to the CIWindow:

 

 0 -> ether_adc45n adc_sample_hold     layout: 
 1 -->    gpdk045  pmoscap2v     layout: |C3
 1 -->    gpdk045  pmoscap2v     layout: |C4
 1 --> ether_adc45n inv_2x_hv_small     layout: |I58
 2 --->    gpdk045     nmos2v     layout: |I58/|NM0
 2 --->    gpdk045     pmos2v     layout: |I58/|PM0

Limiting the Descent

The smpFilterInstances can be implemented for a sub-class to affect which instances get considered for visitation. The documentation for smpFilterInstances is shown above.

The following code defines the class smpSaveDesign and extends the sample GUI, adding the capability to walk the design hierarchy, saving any unsaved cellViews.

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(defclass smpSaveDesign (smpPrintDesign)
   ())

(defmethod smpDescription ((_obj smpSaveDesign))
  (strcat (callNextMethod)
          "\nAnd save any unsaved cellViews."))

(defmethod smpWalk ((_obj smpSaveDesign) cv @rest _otherArgs)
  (callNextMethod)
  (cond
    ((member cv~>mode '("r" "s"))
     nil)
    ((cv~>modifiedButNotSaved)
     (dbSave cv))))

(defmethod smpFilterInstances ((obj smpSaveDesign) cv)
  (foreach mapcan ih cv~>instHeaders
    (when ih~>instances
      (ncons (car ih~>instances)))))

(smpAddClass 'smpSaveDesign)

In this example a method on smpWalk which saves the cellView if needed. It doesn't try to save cellViews which are read-only, nor scratch cellViews. Also it doesn't try to save anything unless it has modifiedButNotSaved set.

The smpWalk method specializing on smpDescendDesign calls smpFilterInstances to determine the list of instances to consider for descent. A smpFilterInstances method on smpSaveDesign is added here, which DOES NOT call callNextMethod. Since we are descending the hierarchy to save unsaved cellViews, we don't need to visit the same master more than once. This method returns a list of instances in the given cellView, one per instance header, which has an instance. I.e., sometimes instHead~>instances is nil; these are skipped.

Descending a Schematic Hierarchy

The classes shown above are great for walking a layout hierarchy. At each step the smpWalk is called recursively on the master of the instance being examined. To descend a schematic hierarchy, we ignore the master of the instance which is probably the symbol, and open and descend explicitly into the schematic when it exists. To do this we define the class smpSchematicHierarchy and provide the method smpGetSwitchMaster. See the smpGetSwitchMaster documentation.

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(defclass smpSchematicHierarchy (smpDescendDesign)
   ())

(defmethod smpGetSwitchMaster ((obj smpSchematicHierarchy) inst)
  (when (ddGetObj inst~>libName inst~>cellName "schematic")
    (dbOpenCellViewByType inst~>libName inst~>cellName "schematic")))

(defmethod smpDescription ((_obj smpSchematicHierarchy))
  (strcat (callNextMethod)
          "\nAnd descends a schematic hierarchy by looking for schematic cellviews""\n of symbol instances."))

(smpAddClass 'smpSchematicHierarchy)
The important method implemented here is smpGetSwitchMaster, which tests whether the schematic exists; if so, it opens and returns it. The smpWalk method specializing on smpDescendDesign calls smpGetSwitchMaster to determine which cellView to descend into, if any.

Combining Classes with Multiple Inheritance

SKILL++ supports multiple inheritance. This means a class is in principle allowed to inherit from more than one class.

We can use multiple inheritance to create an option in the sample GUI, which both descends the schematic hierarchy (based on class smpSchematicHierarchy) and prints information as the visiting occurs (based on class smpPrintDesign). To do this we define the class smpPrintSchematic to inherit from both smpPrintDesign and smpSchematicHierarchy, making the graph of the class hierarchy look like the following.

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Here is the code:

(defclass smpPrintSchematic (smpPrintDesign smpSchematicHierarchy)
   ())

(smpAddClass 'smpPrintSchematic)

Notice in this case that we don't define any new methods. This is because the methods defined thus far suffice for what we need. For example: the smpGetSwitchMaster method for class smpSchematicHierarchy will be used. In addition, since they all call callNextMethod of smpWalk for all the classes, (smpPrintDesign, smpSchematicHierarchy, and smpDescendDesign) will be used. In addition when selecting "smpPrintSchematic" on the GUI, we get a concatenated description of all the parent classes of smpPrintSchematic.

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Conclusion

Download this sample SKILL++ application, and load it by loading the startup.ils file. Again you'll need to start the GUI by typing smpGUI() into the CIWindow.

In this article we looked at a SKILL++ application which extends a specially designed application form. The application form allows you to select between several different behaviors based on the name of a selected class.

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The article shows several examples of class and method declarations which extend the given sample application in different ways. In particular it shows some simple examples of:

  • How to create a sub-class of an existing class
  • How to specialize a method on your class
  • How to use callNextMethod
  • How to use simple multiple inheritance

For more specific information on the SKILL++ Object System, please consult the Cadence online documentation. And as always, please post comments or questions below.

See also:

Virtuosity: 12 Things I Learned in November by Browsing Cadence Online Support

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New content on a wide variety of topics in November.

Product Information 

1. Cadence Online Support Release Highlights

Find out about all the new improvements which have been made to the Product Pages on COS.

2. PVE Release Mechanism Change Letter

Changes in the way the Physical Verification System (PVS), QRC Extraction and K2 products are released.

Application Notes

3. Troubleshooting connect module issues with the AMS Designer simulator

Describes different types of problems which may be encountered with connect modules in mixed signal/mixed language simulations, and outlines solutions for each.

4. LEF Abstract Generation for IO cells

Describes how to apply the Abstract Generation tool from the Virtuoso IC6.1.5 stream to build optimized LEF abstracts from scratch for use in the rail analysis in Encounter Power Systems.

5. PVS Multi/Distributed Processing

This document provides an introduction, examples, and troubleshooting tips on the job submission process for multi-processing jobs in the Physical Verification System (PVS) tools.

6. How to Identify and Debug Multi-Stamp Errors with Assura

This document helps designers understand the definition of multi-stamp layout errors, what causes them, and how to debug them using the Assura Physical Verification tool.

Videos

7. Extracted View Parameterization

This video demonstrates a new feature in IC 6.1.6 ISR3, which allows you to parameterize extracted or layout/partial layout views in order to perform simulations and optimization to meet design specs, then back-annotate changed and optimized parameter values to the schematic.

Solutions

8. How to arrange assistant tabs on the side

When you stack assistants in Virtuoso, by default the tabs for selecting the stacked assistants appear on the bottom.  This handy feature switches the tabs to the side to make it easier to select the assistant you need.

9. Simulating designs with Out-of-Module references in AMS Designer

This tutorial presents the methods available for reusing a digital testbench that contains an Out-of-Module reference(s) (OOMR) in an analog-mixed signal (AMS) design simulation where SPICE blocks are substituted for some of the digital blocks.  An OOMR is unique in that it is used to reference from one Verilog module to another module and it does not pass through any of the ports. This is very commonly used in purely digital designs. Since this reference does not pass through the ports, special handling is required to make testbenches containing it work in an AMS simulation.

10. ncelab fails with CMINHD, CMINHR, or CMINHE error in INCISV 12.2 ISR

Explains possible scenarios and suggestions for fixing these errors, which can appear in the new release of INCISV due to unconnected inherited connection terminals.

11. Setting up the new Transmission Line workshop library and rfTlineLib

How to find and set up the necessary files and libraries to explore the new TransmissionLineWorkshop and rfTlineLib components.

Blog

12. ICCAD 2013: The New Electrically Aware Design Paradigm

Article discussing a presentation made at ICCAD on Cadence's Electrically Aware Design tools (EAD).   EAD enables design teams to do electrical verification incrementally in real time as each physical layout design decision is made.

 

Stacy Whiteman


Virtuosity: 15 Things I Learned in December 2013 by Browsing Cadence Online Support

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With this month's title, I'll need to start adding the year, as this marks the one-year anniversary of the montly series.  I know it's been a useful monthly exercise for me.  Hopefully it has been helpful for everyone out there as well.

Application Notes

1. How to Utilize a Windowing Technique for Accurate DFT

Explains the best way to set up a transient simulation in ADE in order to achieve good results when performing DFT frequency analysis.  Includes detailed background explanations, comparisons of different methods, and examples.

2. Efficiently Moving Between ADE L and XL in a Sequential Design

Describes an efficient and effective methodology for moving between ADE L and ADE XL in the context of sequentially performing design tasks.  Explains how to move test setups from ADE L to XL, how to set up sweeps, corners and specifications, and the best way to add and manage multiple testbenches.

3. Exchanging OA database views between Encounter (EDI) and Virtuoso (IC)

Basic things to know when interoperating with physical hierarchy between Encounter and Virtuoso.

Videos

4. Using the SKILL IDE in IC 6.1.6

5. Using the PCell IDE in IC 6.1.6

6. SKILL IDE Workspaces and Assistants

A playlist of 3 videos (all accessed from the same link above) explaining how to use the SKILL IDE (Integrated Development Environment) and the PCell IDE, which provide tools and utilities to assist in the creation and debugging of SKILL programs and PCells.

Rapid Adoption Kits

7. PVS Configurator

This is a workshop on how to use the PVS Configurator to create configuration files for PVS technology rules setup.  Using configuration files and letting the designers make choices and save them for subsequent runs is an effective way to provide the options to the designer. Using a configuration file also lets the designers choose options directly from the main rule file supplied by the foundry. Includes detailed instructions and database.

8. Working with the Binder to stay XL compliant

When working in the Layout XL connectivity-aware environment, it is extremely important to establish and maintain the correct correspondence between the schematic and layout instances.  The Layout XL Binder makes and manages this correspondence, allowing the extractor to propagate the correct connectivity through the design.  This RAK explains how the Layout XL Binder works and how the layout engineer can leverage its capabilities to stay XL compliant and increase productivity.  Includes detailed step-by-step examples and database.

Solutions

9. What is the reelaborateonalter option for in Spectre?

Besides being a poster child for why one should use CamelCaseForLongOptionNames, the reelaborateonalter option can save a lot of evalution time in simulation when you have a long list of alter statements between analyses.

10. VerilogAMS wreal vectors and arrays

Nice explanation of how vectors and arrays are defined and handled in VerilogAMS wreal models.

11. PVS Quick Reference and Frequently Asked Questions

I love these Quick Reference/FAQ documents.  Not only do they usually give a quick answer to "how do I do that?", they also have lots of links to other relevant documents and resources.  This one is a concise document on how to use the PVS tools for LVS, DRC, ERC and several other flavors of alphabet soup.  Be sure to download the whole PDF document referenced in the solution to get all the content, including pictures.

12. Packaging Testcase to Send to Cadence: NEW mmsimpack Utility Replaces getSpectreFiles

Solving the problem of "I'm still missing file abc.xyz" when you have to send a testcase to Customer Support, mmsimpack is a new utility to create a compressed tarfile containing all the input files required for an MMSIM testcase.

Blogs

13. Top Cadence YouTube Videos of 2013

Yes, Cadence does have its own YouTube channel.  Sadly, no dancing kittens or adorable puppies (although I confess I didn't look at every single video), but you will find product video demos, customer success stories, and interviews with industry folks and our own Cadence R&D stars.

14. SpectreRF Tutorials and Appnotes... Shhhh... We Have a NEW Best Kept Secret!

This is the latest refresh in a series which is consistently high on Cadence's list of most-viewed blog posts.  Read it.  You know Tawna would never waste your time.

15. Support for Low Power Mixed Signal Designs in Virtuoso Schematic XL

Gives an overview of new capabilities in the Virtuoso Schematic Editor XL to support CPF (Common Power Format) export, import, and verification to improve productivity in a low-power design flow.

 

Stacy Whiteman

 

What Your Circuit Doesn't Know, Can Kill It!

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Device variation has been a long-standing problem in custom design.  Over the years, our customers have made many attempts to model the behavior though parameterization, simulation model extensions, sub-circuits, and by just "guessing" as to what might happen. As the mathematical complexity of each node increases, so does the difficulty of making sure all the design possibilities are covered during the initial design phases. That's where the Virtuoso Analog Design Environment GXL can be useful. 

Created to use all of the tests and measurements developed inside Virtuoso Analog Design Environment XL, the GXL tool can help you during four distinct design phases: 

1.    Pre-design by helping the engineer retarget existing IP to new processes

2.    In-design by providing a host of sophisticated tools for developing worst case corners, yield improvement mini-flows using matching, tuning, and optimization, and high-yield analysis for discovering circuit behavior at 6-sigma.

3.    During physical implementation by allowing the designer to take "snapshots" of the partial layout to see how parasitics from routing or placement could be skewing the desired results before the design is completed and locked down.

4.    Post-extraction, verifying the design is still meeting specification even after the full hierarchical physical implementation is completed  

With Cadence's unique token licensing within the Virtuoso Analog Design Environment GXL platform, licenses never sit idle since the tokens are flexible enough to cover all of the technology or be used to run ADE XL/L cockpits when not needed for variation design. That makes the adoption of Virtuoso Analog Design GXL easy technically and easy on the budget. Over the next seven weeks, our technical experts here at Cadence will be showcasing six major capabilities contained within the tool:

a.    Creating and using worst case corners

b.    Fast yield analysis and statistical corners

c.    Mismatch variance contribution and yield contribution

d.    Design migration and retargeting

e.    Circuit tuning and optimization

f.    High yield analysis and optimization 

Check into the Custom IC Community regularly to see the latest information. And please speak with your Cadence representative to learn more about the Cadence offerings or to see a demonstration of how the technology can help you.  If you haven't looked at Virtuoso Analog Design Environment GXL in awhile, then you don't know what you are missing!  Let us show you today.

 

Steve Lewis

What's the Worst that Could Happen?: Worst-Case Corners in ADE GXL

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In addition to combinations of temperature range and power supply voltages (usually more than one), the process design kit which landed on your desk yesterday presented a bewildering alphabet soup of device corner combinations which you need to consider when verifying your circuit design. 

Fast/slow, high/low, pre/post.  If I have to spend the time to run all the possible combinations, I won't have much time left to tune my design. But how do I really know which combinations are going to be the worst case for each of my specifications? 

This is exactly the problem addressed with the Worst-Case Corners (WCC) run mode in the Virtuoso Analog Design Environment GXL (ADE GXL). 

The approach is straightforward, the setup is simple, and the results are powerful.

The Approach-Framing the Problem

Worst-Case Corners follows a basic Design of Experiments (DoE) methodology.  That is, given a set of input variables (your corner parameters and their values), and a set of measured output responses (your testbench measurements), a number of trial sets of input values are intelligently chosen and simulated. The results are observed and analyzed and then one corner is created for each specification containing the combination of variable values which has been determined to give the "worst" result.  (Two worst corners are created for range and tolerance type specs.)

In general, process corners are given special treatment during trial creation, since there is inherently no natural sequence to the list of model sections. Thus, all process corners are considered in simulation.

The Setup-What Goes In?

WCC works with your existing ADE XL testbenches, measurements and specifications.  You can use the corners you already have defined in ADE XL as input for the WCC setup, or you can specify any combination of variable values to be considered.

Several methods are provided to trial experiment selection and corner creation. You choose the method based on the linearity of your circuit response and inter-relationships of your input variables.  Standard DoE and response surface methods (RSM), such as one-factor-at-a-time (OFAT), Central Composite and Factorial, are supported to give a full spectrum of analysis capabilities and performance. 

The number of simulations required to determine the worst-case corners depends on the number of variables and the number of values for each variable.  Typically, on the order of 30-50 simulations are run for most common corner setups.

The Results-What Comes Out?

At the conclusion of a run, worst-case corners are created for each specification in your ADE XL setup.  Depending on the method used, the created corners will be simulated and validated against the models used to identify the worst-case variable values.

In addition, the results of the simulations are analyzed for sensitivity and displayed in an interactive table, allowing you to further examine the characteristics of your circuit's responses to each variable as well as how each factor contributes to the overall variation in circuit performance.

Now that you have created the worst-case corners for your design, you are well-positioned to efficiently optimize your design, either manually using ADE XL, or by taking advantage of advanced ADE GXL analyses such as Sensitivity Analysis and Circuit Optimization.

Virtuosity: 14 Things I Learned in January and February 2014 by Browsing Cadence Online Support

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Time just got away from me last month, so here's two months worth of new content for your browsing enjoyment...

Videos

1. Integration Constraints Capability used in Mixed Signal Design Implementation

Explains and demonstrates the integration constraints capability of the Cadence Mixed-Signal Solution.

2. Virtuoso Floorplanning Design Flow Demo

Demonstrates the Virtuoso Floorplanner Flow: soft and hard blocks, defining cell type attributes, configure physical hierarchy (CPH) – soft block parameters, generate physical hierarchy, block placer, snap pins, editing soft blocks, and pin optimization.

Rapid Adoption Kits

3. Electrically Aware Design (EAD) Workshop

Covers the main functionality of EAD, which is a flow that allows extraction of layout parasitics at any point in the design cycle.  You can resimulate with parasitic effects using layouts that are incomplete.  This flow also supports electromigration analysis based on Spectre simulation results. Includes detailed tutorial and database.

4. IC 6.1.6 Pin To Trunk Device-Level Routing

Steps through the Pin to Trunk Device-Level Routing Flow in Virtuoso in IC6.1.6 ISR4.  This flow enables users to quickly connect device pins in a structured topology.  Includes detailed tutorial and database.

5. IC 6.1.6 Pin To Trunk Block-Level Routing

Steps through the Pin to Trunk Block-Level Routing Flow in Virtuoso in IC6.1.6 ISR4.  This flow enables users to quickly connect block pins in a structured topology.  Includes detailed tutorial and database.

Solutions

6. Fluid Guard Ring Frequently Asked Questions

This is a compilation of the most popular solutions related to fluid guard rings.

7. AMS Designer in ADE FAQ

Answers to customer's most frequently asked questions about the interface to the Virtuoso AMS Designer Simulator in ADE.

8. BindKey Quick Reference in Virtuoso Schematic Editor

A handy chart of all the default bindkeys for the Virtuoso Schematic Editor--single key, Ctrl, Shift and Ctrl-Shift versions, plus function keys--in a concise keyboard layout.

9. bindKey Quick Reference Guide for Virtuoso Layout Editor

A handy chart of all the default bindkeys for the Virtuoso Layout Editor--single key, Ctrl, Shift and Ctrl-Shift versions, plus function keys--in a concise keyboard layout.

10. How to print Monte Carlo statistical parameters greater than 1900 in ADE XL?

A little piece of SKILL code to dump all the values of statistical parameters for each point in a Monte Carlo run to a CSV file.

11. PVS Quick Reference and Frequently Asked Questions

Concise and handy quick reference document on how to use the PVS tools to work with designs, including how to verify a layout against physical design rules and schematics.

Blog Articles

12. Have You Tried the New Transmission Line Library (rfTlineLib)?

An overview of the new RF transmission line library in IC6.1.6 ISR1, which contains wideband-accurate transmission line models in multi-conductor microstrip and stripline configurations.  They are integrated in Virtuoso ADE and accessible from stand-alone Spectre netlists.

13. What Your Circuit Doesn't Know, Can Kill It!

Introduces an upcoming series of articles covering the advanced capabilities of Virtuoso Analog Design Environment GXL to handle variation-aware design issues, such as finding worst-case PVT corners, performing efficient statistical and mismatch analysis, circuit optimization and design migration.

14. What's the Worst That Could Happen?: Worst Case Corners in ADE GXL

This is the first in the above-mentioned series of articles and covers an ADE GXL analysis which enables you to quickly identify the worst case PVT corners for each of your design specifications so you can save time during design iterations and ensure your design is robust.

 

Stacy Whiteman

Fast Yield Analysis and Statistical Corners

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The Virtuoso Analog Design Environment XL Monte Carlo sampling methods are Random, Latin Hypercube, and Low Discrepancy Sequence.  More accurately, Spectre provides the engine and ADE XL interfaces with the simulator to complete the Monte Carlo analysis task.  Random is the standard random sampling method.  Latin Hypercube (LHS) is an enhanced method that converges faster.  Low Discrepancy Sequence (LDS) is the most recently developed method.  Experimental results that compare the three methods are shown in the figure below.

Phase Margin of an op amp is measured and the mean error is compared to the golden result of 100K Monte Carlo samples.  Each data point represents the result of 20 independent trials.  The mean error is:

This is only one example but, in general, LHS and LDS results are found to be comparable.  An advantage of LDS over LHS is that it is compatible with the ADE XL feature to automatically stop the Monte Carlo run given a yield estimate target.  Provide a yield target and Monte Carlo will stop performing simulations when the design is either found to exceed the target or found to be low yield.  This saves time by not running any more simulations than necessary based on the specified significance level.  If needed you can loosen the significance level to get results faster or increase the level depending on your requirements.

 


Once the Monte Carlo results are available, statistical corners can be created.  In ADE XL you can create a statistical corner from any of the simulated samples.  There are several options to create the corner, including selecting a point on the histogram, creating a corner out of the worst sample, or by percentile.

ADE XL saves only the relevant information such as seed, sequence number, sampling method, etc. with the corner. Spectre can then recreate the statistical parameter values for the corner from this information. This type of corner is efficient and does not require that all the statistical parameter data for each sample is saved in Monte Carlo.  The downside is that some changes to the design topology such as the addition of a new instance to the schematic can invalidate the corner.  The simulator can no longer recreate the same set of statistical parameter values when simulating the statistical corner.  Two types of statistical corners are possible in ADE XL with version IC6.1.6 ISR6; a corner with the sequence info saved, or a corner that contains all of the statistical parameter values.  The values-based corner is more robust in the face of these minor design changes. The new instance added to the design does not invalidate the existing statistical corner of this type. The user can choose which corner type better suits their needs.

All of the above methods define the corner by one of the simulated Monte Carlo samples.  To create a 3 sigma statistical corner you must have simulated a large number of samples.  A new ADE GXL feature to be released with IC6.1.6 ISR6 addresses this problem.  The goal is to create a k sigma statistical corner quickly (by default 3 sigma - you can specify the yield-in-sigma target) without the need to run thousands of simulations.  The fast 3 sigma corner flow is to:

  • Run Monte Carlo (only a few hundred samples compared with the traditional approach requiring 1000+ samples)
  • Create the fast 3 sigma statistical corner

A minimum of 1 and a maximum of 11 extra simulations per corner are needed for this step.

The fast 3 sigma corner algorithm estimates the probability density function (PDF) of the performance distribution maintaining accuracy for non-normal distributions.  The specification target value is computed from the PDF estimate.

A statistical corner is then created that matches the target spec value.  There can be multiple corners that meet this criteria.  This method finds the most representative corner by minimizing the distance to the nominal point.  This representative corner has a greater probability to occur.  Now the statistical corner can be used for further analysis of the design.  Look for this feature in ADE GXL in the next IC6.1.6 release.

 

Lorenz Neureuter

Efficient Design Migration Using Virtuoso Analog Design Environment GXL

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Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes.  However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects, often from one process node to another.  Additionally, migration is also required for:

  • Second sourcing on a similar process from a different foundry
  • Reusing IP in next-generation process nodes
  • Providing variant IPs with different requirements

Migration of analog circuits is often a cumbersome and designer-intensive process.  When migrating a block that has already been designed, verified, and tested to a new process, it is often desirable to maintain the same architecture and in many cases the same or similar circuit performance of the original source design. The following provides an overview of a methodology for performing such a process migration for schematics and testbenches.

Cadence's Virtuoso Design Migration flow consists of:

  • Validation of source circuit performance
  • Schematic migration
  • Assessment of target circuit performance
  • Optimization of target circuit to achieve desired performance

The Virtuoso Design Migration flow is a methodology-driven activity, assisted by automation.There are three major phases - PDK and design assessment, design environment preparation, and design migration and verification.The software used to assist the user is contained within Cadence Virtuoso Analog Design Environment GXL as a part of the optimization tool suite.

PDK and Design Assessment

Before relying on assisted automation, a successful migration requires a careful assessment of both the source and target Process Design Kits (PDKs).  This assessment will help to determine the level of automation that can be applied to the migration or re-design required by determining device correspondence between the source PDK and the target PDK. Once a device correspondence is established, there are several challenges that will determine how well the source design can be migrated. Some of these challenges include symbol compatibility, mapping of passive devices (which can result in fairly large changes in layout area), and design type as this will dictate the level of automation which can be applied during migration. For example, migration of analog blocks function with rail-to-rail voltage margin can be automated significantly more than RF blocks or blocks which are affected by low voltage differences.

Design Migration and Verification

The design migration process starts by replacing the source PDK devices with the mapped devices from the target PDK in each block to be migrated.  This is typically a fairly automated process. The target schematic is then substituted into the testbench schematic. Following migration, the verification plan which was run on the source design is rerun on the target design. The results are compared against the specifications and against the performance of the source design.  If necessary, the block can be optimized to achieve compliance with the specification.

The diagram below outlines a typical front-end migration flow.

A workshop is available which demonstrates this methodology and provides additional details.  You can contact your local Applications Engineer to access this workshop or for additional assistance.

 

Tom Volden

Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

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When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. You can also compare the relative importance of the contributing instances.  The analysis results can aid in making design changes to reduce the variation.  Mismatch Contribution is a variance-based global sensitivity analysis [1].

Mismatch Contribution is launched from Monte Carlo results.

 Here is a flat view of the outputs, and mismatch parameters are displayed and sorted by the swing specification.

Each device instance may be modeled with multiple statistical mismatch parameters.  The parameter names themselves are not always of interest.  In some cases the PDK models are derived from principal components.  Mismatch Contribution provides a hierarchical view where the total contribution of all of the device parameters is displayed for each instance.  The hierarchical view reports the contributions by instance for quick identification of important instances.

Cross probing to the schematic is provided.  The schematic is opened to the same level of hierarchy, and the selected instances are highlighted.  Navigate the table as you would a schematic.  Descend into a row (instance) of the table until reaching the leaf level.  The leaf level again displays the individual mismatch parameters of the instance.

By contrast, a top-level view with four blocks shows the block contributing the most variation of the specification.  Descend to find the lower-level contributors.

When global process variation is applied during the Monte Carlo analysis, the contributions from the process parameters are included in the contribution analysis.

Mismatch Contribution is not limited to linear effects.  When a linear model of the data is insufficient, a quadratic model is automatically applied.  The R^2 value in the header of the table for each specification is the proportion of variance explained by the model.  This is the goodness of fit of the model.  Sparse regression techniques allow for computation of the contributions even when the number of parameters is very large compared to the number of Monte Carlo samples simulated [2].

Mismatch Contribution is available now in Virtuoso ADE GXL, first released in IC6.1.6 ISR3.

[1] http://en.wikipedia.org/wiki/Variance-based_sensitivity_analysis 
[2] J. Tropp and A. Gilbert, "Signal recovery from random measurements via orthogonal matching pursuit," IEEE Trans. Information Theory, vol. 53, no. 12, pp. 4655--4666, 2007.

 

Lorenz Neureuter


What's New(-ish) in ADE XL in IC 616 ISR 3?

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Development Model for ADE and ViVA

Virtuoso Analog Design Environment (ADE) and ViVA follow a development model that allows new content to be added in every third ISR.  These content ISRs receive additional usability testing, product validation, and demonstrations and beta testing with customers. This development model gives R&D long enough development cycles to add meaningful content while ensuring that quality and stability of the main ISR stream is not compromised.

While this development model provides an excellent method to deploy new features and functionality in a frequent but controlled manner, it also presents challenges in making customers aware of the new capabilities.  This blog post outlines some of the new features that first appeared in ISR 3, which was released in November (hence the "-ish" in the blog title).  The next content release, ISR 6, will be available at the end of April so look for a fresh post with additional new items soon.

So let's get too it!  What's New(-ish) in ADE XL in 616 ISR 3?

  • Performance and stability improvements when working with a large number of corners
  • Better handling of disk full and other conditions which previously resulted in crashes
  • Usability improvements in Annotation Balloons based on user feedback
  • Ability to add user defined columns in ADE XL outputs setup and results table
  • Allowing individual ICRP processes to be stopped and resubmitted
  • Improved error debugging and access to job log
  • Setting default results view for single run, sweeps and corners
  • Measurements tied more tightly to analyses
  • Improved use model for pre-run scripts
  • More efficient use of disk space when a netlist is re-used for all points
  • Low Discrepancy Sequence (LDS) sampling method support for Monte Carlo
  • Ability to launch Debug Environment for Monte Carlo points
  • Sample points displayed on histograms with cross selection to ADE XL results table

What new feature are you most excited to see?  Are there other features that you would like to have to make your job easier?  Do you have questions about ADE XL or other Virtuoso products?  Leave a comment  below and I will try to address them in future blog posts.  Also watch this space for details about new features in ISR 6 when it is released at the end of the month.

Tom Volden

Virtuosity: 15 Things I Learned in March 2014 by Browsing Cadence Online Support

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Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL.

Application Notes

1. Physical Verification Checks and Generic Tips

Concise overview explaining the basics of the various DRC and LVS checks in rules files.

2. Recommendations and Tips for the PVS DRC Flow

Includes sections on preparation of runsets, running DRC, preparation of design blocks and DRC/LVS check of top-level GDS.

3. Recommendations and Tips for the PVS LVS Flow

Design and runset preparation, links to helpful solutions and sources of common errors.

4. Recommendations and Tips for the PVS Metal Fill Flow

Preparation of runsets, working with different fill scenarios and how to correct errors.

Rapid Adoption Kits

5. Making a layout XL-compliant using Update Binding (XLME)

Uses a sample design scenario to explain how the Update Binding command can be used to increase the VLS XL-compliance of a design using the physical connectivity in the layout and the output from a PVS LVS run. 

6. PSPICE netlist support in ADE

Describes the integration support in Analog Design Environment (ADE) to include a netlist in PSPICE format.

Solutions

7. Why isn't there an hbxf in the Choosing Analyses form?

You have recently started using the GUI for hb analysis and the associated small signal analyses. You noticed that there is a periodic xf (pxf) small signal analysis for pss. Why isn't there a similar analysis (hbxf) for hb?  Click on the link to find out.

8. Is PSF-XL supported for AMS simulation?

(Spoiler Alert) Why yes.  Yes it is.  This solution will tell you how to use this faster analog waveform format. 

9. Why do we have mulitple MMSIM13.1 hotfixes on downloads?

Several MMSIM 13.1 hotfix versions are being maintained on downloads to accommodate specific foundry/PDK rollouts.  Click the link for more information.

10. How to create a form showing a thumbnail image of the cellView

Wow, this could be fun.  A while ago, I wrote an article about how to create thumbnail images.  Now you can find out how to include those images in your own forms.

11. Does bindkey work with forms?

This solution provides an example of how to create a form in which you can register your own set of bindkeys.

12. How to create a custom RAP generator that creates additional constraints?

I would like to modify the existing CurrentMirror generator code to create additional constraints, for example, orientation and matched parameter constraints in addition to the modgen constraint. Here is that sample code.

Blogs

13. Fast Yield and Statistical Corners

Describes the different sampling methods available in ADE XL Monte Carlo analysis, the advantages of using auto-stop if you don't know how many samples are needed, and the types of statistical corners that can be created from the Monte Carlo results to help the designer improve circuit yield.

14. Efficient Design Migration Using Virtuoso Analog Design Environment GXL

The article provides an overview of a methodology for performing process migration for schematics and testbenches, including PDK and design assessment, design migration and final verification.

15. Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. The article describes the concepts behind this analysis how to use it.

Stacy Whiteman

Keeping Your Circuit in Tune: Sensitivity Analysis and Circuit Optimization

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Anyone who has ever played a musical instrument knows how hard it can be to keep the instrument in tune when subjected to variations in weather conditions. Heck, in 2009, Yo-Yo Ma and friends (sorry, he gets top billing because I used to play the cello) pantomimed their performance at the Presidential Inauguration because their instruments wouldn't function properly in the frigid temperatures. Guess they didn't want to risk sounding like my seventh-grade orchestra in front of that large an audience. 

Well, we've been talking a lot in this blog recently about the problems caused by the effects of variation on circuit design, and the risks of being "out of tune" can be just as great when it means your chip is late or doesn't work properly.

Today we're going to talk about some of the features available in the Virtuoso Analog Design Environment GXL (ADE GXL) to help you tune your circuit to overcome the effects of variation on circuit performance. Let's start by putting things in the context of an overall flow that looks like this:

Setup and Corner Creation

The basic idea here is that you start with a test setup in ADE XL, which can consist of multiple testbenches, each with a set of output measurements and design specifications. Then you add the relevant corners, which will cover the limits of the design performance across which you need to optimize. These can be your standard PVT corners, they can be a critical subset of corners generated using the ADE GXL Worst Case Corners analysis, or they can be statistical corners generated from a Monte Carlo analysis to capture 3-sigma or other outlying statistical behavior for each of your design specifications. 

Parameterization

One of the keys to getting the most out of the circuit-tuning capabilities in ADE XL and ADE GXL is device parameterization. I've written about this feature before, but to recap, the Variables and Parameters Assistant in ADE XL allows you to create parameters for any device properties and vary them at will without having to edit the schematic. You can also incorporate critical device matching and ratioing relationships. 

The "Create Parameter Range" option will automatically create a +/-% range on any parameters, which makes sensitivity analysis and optimization a snap.

Sensitivity Analysis

Sensitivity Analysis in ADE GXL allows you to get a good idea of the criticial devices in your circuit and their effects on design performance. With only a few targeted simulations, you can find out which devices in your circuit have the most impact on each of your design specifications, as well as how changing a device size whether changing a device size to improve one spec will adversely change the other specs.  Device parameterization makes it quick and easy to evaluate "what-if" scenarios until your desired performance is achieved.

Local and Global Optimization

The optimization algorithms in ADE GXL have been proven within our customer base for many years. The optimizer works across all the multiple testbenches, specifications, and corners you already have set up, including the worst-case PVT and statistical corners you have defined to capture the extreme boundaries of your circuit behavior. Device parameters are intelligently varied over the ranges you have defined until all design specifications have been met. Simulations are distributed using ADE XL's job distribution system to maximize the efficiency of the analysis.

ADE GXL provides four local optimization algorithms: BFGS (recommended for most common analog circuits), Conjugate Gradient, Brent-Powell, and Hooke-Jeeves. Use these when you have a reasonable degree of confidence in your initial circuit starting point values. If you aren't sure of your starting point, use Global Optimization, which will perform a much broader exploration of the design space to find viable circuit solutions.

Several additional optimization-based run modes are available, including Size Over Corners to efficiently optimize over a large number of corners and Improve Yield, which combines Monte Carlo analysis and automatic statistical corner creation with iterations of circuit optimization to center your design within statistical process and mismatch variation.

Verification

"The proof of the pudding", as they say, "is in the eating," so the final step in our big red PowerPoint SmartArt arrow above is to verify the results of the circuit tuning. This may involve running a final simulation across all PVT corners or a final Monte Carlo analysis to verify the optimized design can overcome the effects of all types of variation.

 

What’s New in Virtuoso ADE XL in IC616 ISR6?

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In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3.  Here are more new features that are now available in Virtuoso ADE XL in the recently released ISR6.

  • Notes can be added to tests, variables, corners, parameters, and histories. This allows you to document information about important items in your setup or make notes about a particular history to document simulation conditions, results, or other key information.
  • Comma separated value (CSV) files can now be used to import and export corners setup. This improves the use model for managing corner setups in external editors. Prior to this enhancement, import/export required the use of more complicated XML format from the Virtuoso ADE XL setup database (SDB).
  • Ability to cancel selected tests and corner points. Previously, stopping a run canceled all running and pending simulations. The new feature allows you to selectively cancel individual simulation for a particular corner or test. Remaining tests and corners will continue to be run.
  • Creation of K-sigma corners from limited Monte Carlo samples. The new algorithm estimates the Probability Density Function and computes the corner specification value based on that PDF. A statistical corner that matches the target specification value is then created. This is an improvement over previous methods for creating statistical corners with a particular standard deviation as they required a large number of Monte Carlo points to achieve accurate results.
  • Ability to filter evaluation and simulations errors from yield estimate in Monte Carlo simulations
  • Wild card selection is now supported in the Annotation Setup form
  • Value-based statistical corner creation from Monte Carlo simulation is available. This allows the distribution point to be maintained with minor changes to the design such as addition of new device instances. Prior to this, any changes to the design which impacted connectivity would invalidate the statistical corner.

What new feature are you most excited to see?  Are there other features that you would like to have to make your job easier?  Do you have questions about Virtuoso ADE XL or other Virtuoso products?  Leave a comment  below and I will try to address them in future blog posts.

 

Tom Volden

High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma

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Why high yield analysis?

One failed memory cell out of millions cells will cause the whole memory circuit to fail without ECC (error checking and correction) techniques. That is why memory designers have high parametric yield requirements for the SRAM core cell. It requires no fails in hundreds of millions or billions of brutal force Monte Carlo simulations if foundry statistical models are accurate up to the high sigma region.Memory circuit designers also have high yield requirements for other circuit block and memory partitions, such as sense amplifier sor critical-path partitions.

 

How to analyze high yield and debug, improve the design in Virtuoso ADE

Virtuoso Analog Design Environment GXL selects WCD (worst case distance) metric-based method as its high yield solution. To estimate high yield, ADE GXL will first find the WCD point in the statistical space.Once the WCD point is found, the yield can be calculated directly using the WCD.

 


 

The accuracy of WCD is impacted by nonlinearity of spec boundary in statistical spaces. However, that error is not significant in most high yield applications. The WCD point has the shortest distance from nominal point to fail region in statistical space. It is also the most probable point to fail in statistical space. During a continuously running Monte Carlo process, the first failing Monte Carlo point has a very high probability to be very close to the WCD point in statistical space.This makes the WCD point very attractive for creating a high-yield statistical corner because it captures the circuit condition with the highest probability to fail.This point becomes increasingly important if designers want to debug and improve the design. Based on the WCD point, Virtuoso ADE GXL provides the capability to create a high-sigma corner to improve the yield. 

 


The completed high yield solution in Virtuoso ADE GXL is a part of the TSMC AMS reference flow. It includes:

1.    High yield calculation

2.    Creation of high yield statistical corner

3.    Optimization of the design with high yield corner

4.    Verification of design using high yield calculation


 

 

What is coming next? New algorithms for high dimension!

Cadence R&D co-invented the next-generation high yield estimation algorithm with researchers from Carnegie Mellon University recently[1]. The scaled-sigma sampling algorithm works well with high-dimensional nonlinear problems, which exist in large circuit blocks. Please stay tuned!. The algorithm will be publicly available in the coming IC616ISR release.

 

[1] Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo and Ben Gu, "Fast statistical analysis of rare circuit failure events via scaled-sigma sampling for high-dimensional variation space," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 478-485, 2013.

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