Virtuosity: Organizing Waveform Families
Virtuosity: Using the Expression Builder to Plot across All Corners and Points
The Expression Builder has simplified writing complex expressions and has the ability to plot or evaluate particular points and corners. But we wanted it to do more, recently we added the ability to plot or evaluate across all points and/or all corners.
This makes it really easy to see your plots across sweeps or corners from different histories or tests.
There are new options for All under the Point and Corner drop-downs.
So this makes it easy to plot this clip expression for one point across all corners:
Or one corner across all points:
Or all points across all corners:
Tables
Related Resources
- Blogs
- Videos
- Rapid Adoption Kit
About Virtuosity
Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts. Happy Reading!
Virtuosity: CDNLive India—Our Window to KYC!
In line with the recently-implemented mandate in India requiring banks and financial institutions to regularly run “Know Your Customer (KYC)” cycles, CDNLive India has become a reliable event for the Technical Communications Engineering team to regularly touch base with customers, and to ensure the team knows their customers in order to exceed customer expectations.
The Publications Infrastructure and CPG Technical Communications teams, both a part of Technical Communications Engineering, jointly ran a “booth” during CDNLive in India. The main attraction for the approximately 100 Cadence customers who visited the team was the upcoming Cadence Help 3.0 release, with its much-enhanced search functionality and improved performance. A big draw was the impressive desk calendar that the visitors could win by correctly answering questions to a quiz based on upcoming Cadence Help functionality. All visitors gained from the live demonstration and preview of the new help functionalities.
Not only was the event a win-win for customers, the Cadence representative teams had much to gain from first-hand views on what customers think about the next planned Cadence Help upgrade, and future online delivery platform the team is targeting. The teams captured customer pulse through an online survey and engaged with experienced and relatively new Cadence product users to fully understand customer requirements in terms of content accessibility, the infrastructure these organizations support, and their overall organizational setup.
Together, the online survey findings and the information gathered by the team through detailed discussions with stakeholders from small and large customer accounts gave a good window to explore what’s possible. The team is now using the collated data to validate their assumptions and plans about future CH upgrades, and is meticulously running through the collated information.
While it wasn’t on the agenda, the team also gathered customer feedback on Cadence content, content delivery and accessibility, and preferences. The team also took the opportunity to educate customers about blogs, more specifically about Virtuosity and Virtuoso Video Diary blogs that are collaboratively being written by the CPG Technical Communications team and other members of the cross-functional teams.
- Rishu Misri Jaggi
Virtuosity: Can I Plot Signals with Different Axis Units in the Same Window?
Virtuosity: SKILLful ViVA – The Champion of Graph Analysis
Virtuosity: Can I Graphically Edit Width Spacing Patterns?
Virtuosity: From Hatchlings to Fledglings to a Flock of Birds Blogging Together
Virtuosity and Virtuoso Video Diary: Onwards and Upwards
Virtuosity:Expression Builder - Now Plots ALL!
Virtuosity: Sharing Custom SKILL Calculator Functions
Virtuoso Video Diary: Stranded Wire – A New Sapling in Interactive Routing
In order to drive high current and to minimize routing resistivity, it is desirable to draw wide wires. But, in mature nodes, maximum width or maximum density constraints on some metal layers prevent the designers to create wide wires. Another challenge when working with designs at advanced nodes less than 22nm is that it is only possible to route with wires at minimum width. This leads to situations where the current density or the max resistivity cannot be met.
A solution to this is: Stranded Wire
What is a Stranded Wire?
To describe stranded wire in layman's language:
Stranded Wire is composed of a number of small wires bundled or wrapped together to form a larger conductor. See the figure below.
So, in interactive routing, stranded wire is an easy way to create multiple wires at the same time on same net with built-in features to control resistance and metal density. The stranded wire feature is available in Layout XL, GXL, and EAD tiers and was introduced in the IC6.1.7 and ICADV 12.3 ISR9 releases. To access the Create Stranded Wire command, choose Create – Wiring – Stranded Wire.
A stranded wire can be created from the following starting points:
- An empty space
- An existing single pin
- An existing wire or via
- An existing width spacing pattern
You can create the following kind of structure by using the Create Stranded Wire command.
New Videos
Did you know that we retain only 10% of what we read and 95% of what we see?
Therefore, to help you understand and get started with the Stranded Wire new features easily, we bring to you some interesting and informative videos on this topic.
Stranded Wire Support in Virtuoso and Virtuoso Advanced Nodes
This video demonstrates the basic features and bindkey controls of stranded wire.
- What is a stranded wire?
- Why do we need a stranded wire in Layout?
- How to create a stranded wire in Virtuoso layout?
- What are the stranded wire bindkey controls?
- How to terminate a stranded wire?
Stranded Wire Additional Editing Features
This video demonstrates the following editing features of stranded wire.
- Inserting Vias Automatically on Pins and Overlaps
- Using the Stranded Wire Context-sensitive Menu
- Tapering in Stranded Wire
- Creating a Stranded Wire from Tieout
Stranded Wire Advanced Node Editing Features
This video demonstrates the following editing features of stranded wire for advanced nodes.
- WSP Support in Stranded Wire
- Automatic Via Insertion at Bends
- Blockage Avoidance
- Interactive Coloring in Stranded Wire
Related Resources
Virtuoso Space-based Router User Guide
Virtuoso Layout Suite SKILL Reference
Environment Variables
Note: For more information on Cadence circuit design products and services, visit www.cadence.com.
About Virtuoso Video Diary
Virtuoso Video Diary is an online journal that relays information about Virtuoso videos that are available in the Cadence Online Support Video Library. Hundreds of interesting videos on a wide variety of new and exciting Virtuoso features have already been created. Virtuoso Video Diary brings you direct links to these videos and other related material, on regular basis. Click Subscribe to visit the Subscription box at the top of the page in which you can submit your e-mail address to receive notifications about our latest Video Diary posts.
Happy Reading!
Parul Agarwal
Virtuoso Video Diary: Self-Paced Learning through Training Bytes
Virtuosity: New Eye Diagram Measurements
Virtuosity: Do I Need To Run a Simulation To Plot From a Text File?
Virtuosity: Signal Browsing Gets Easier with Advanced Search Options
Dealing with AOCVs in SRAMs
Systems on Chip, or SoCs as they’re more commonly called, have become increasingly more complex, and incorporate a dizzying array of functionality to keep up with the evolving trends of technology. Today’s SoCs are humongous multi-billion-gate designs with huge memories to enable complex and high-performance functions that are executed on them. It is quite common to have about 40% of an SoC’s real estate used for Static Random Access Memory (SRAM). SRAM design is a complex and highly sensitive process, and what we want to design in the silicon is often different from what actually comes out of the manufacturing process. This is due to Advanced On-Chip Variations, or AOCVs.
AOCVs occur in the device manufacturing processes, and there are two kinds:
- Systematic Variations: These are caused by variations in gate oxide thickness, implant doses and metal or dielectric thickness. They are deterministic in nature, and exhibit spatial correlation – i.e., they are proportional to the cell location of the path being analyzed.
- Random Variations: These are random, as the name suggests, and therefore are non-deterministic. They are proportional to the logic depth of the path being analyzed, and tend to statistically cancel each other out given a long enough path.
As can be deduced, the effects of these variations are getting more pronounced as process geometries are shrinking, and so dealing with them in an effective manner is crucial to the proper functioning of an SoC. And therein lies the rub.
Traditional Solutions for AOCVs in SRAMs
AOCVs need to be modeled effectively, so their effects can be taken into account for the ultimate SRAM design to be successful. This means the design needs to be simulated to account for the random and deterministic process variations. Most companies deal with this in one of the following two ways:
- Running a Monte Carlo simulation on the full memory instance RC extracted netlist
This approach involves creating a simulatable instance netlist from the instance schematic, and running Monte Carlo simulations on the complete netlist, multiple times. This will give us the most accurate results. However, this is an incredibly CPU and memory intensive approach, with run times lasting several days. Additionally, it will require huge runtime memory requirements and will need bigger LSF machines.
- Run Monte Carlo simulations on the critical path RC netlist
This approach involves reducing the netlist drastically by identifying repetitive cells in the memory and replacing them with a load model. Then you create a critical path schematic for each component to be simulated and run Monte Carlo. While this approach is definitely much faster than the previous approach, it still involves several thousand nodes and instances, and runtime is still in the order of a few days. Additionally, it requires time to create critical path schematics for different components and to ensure the setup is correct. Creating a critical path involves manual effort and is error prone, making it a less than ideal solution.
So what is a designer to do?
Enter, the approach used by our customer, Invecas. Their solution is based entirely on the Legato Memory Solution, specifically Liberate-MX runs, with Spectre simulations. It relies on re-suing the characterization database from Liberate-MX runs. This means, there is no additional time spent on setting up the environment. It also involves reusing the partition netlist created by the Liberate-MX flow. Liberate has the inbuilt intelligence of identifying the dynamic partition, and activity factor. This approach results in the least amount of runtime and memory required.
So how does this work?
Liberate runs a Fast-SPICE tool under the hood to identify the worst-case path that is active and toggling, and extracts only that path to work on. Then an accurate SPICE run is performed, to provide the accurate .libs. Generating these accurate .libs is already included in the Liberate MX flow and available today. Invecas then modified this flow for AOCV, by taking this partition, with all the accompanying setups and nodes, and adding a couple of commands for Monte Carlo runs. The script now runs Monte Carlo on the greatly reduced partition, and returns AOCV models with all the derating values in a matter of hours, instead of days, or even weeks.
The comparison of results between the three approaches can be summarized below.
Method 1 FULL INSTANCE SIMS (Considers 300MC runs) | Method 2 CRITICAL PATH SIMS | Invecas Method PARTITION NETLIST SIMS | Invecas Method Improvement over Method 1 | Invecas Method Improvement over Method 2 | |
No.of Devices | 7440000 | 17000 | 560 | 13285.71 | 30.36 |
No.of Nodes | 22400000 | 317000 | 12300 | 1821.14 | 25.77 |
No.of RC elements | 22000000 | 231000 | 12000 | 1833.33 | 19.25 |
RUN Time (Hours) | 350 | 84 | 1.45 | 241.38 | 57.93 |
RUN Memory (GB) | 50 | 10 | 1 | 50 | 10 |
The side-by-side testing clearly shows, that the Invecas method using the Legato Memory Solution has greatly reduced the number of devices, nodes and RC elements that the Monte Carlo run uses, from several million, to a few thousand. This automatically reduces the runtime and memory requirements by several orders of magnitude, thereby solving the biggest problem faced by the designers today.
Please visit our page to find out more about this process, or to read about the Cadence Legato Memory Solution.
Virtuosity: Organizing Waveform Families
Virtuosity: CDNLive India—Our Window to KYC!
In line with the recently-implemented mandate in India requiring banks and financial institutions to regularly run “Know Your Customer (KYC)” cycles, CDNLive India has become a reliable event for the Technical Communications Engineering team to regularly touch base with customers, and to ensure the team knows their customers in order to exceed customer expectations.
The Publications Infrastructure and CPG Technical Communications teams, both a part of Technical Communications Engineering, jointly ran a “booth” during CDNLive in India. The main attraction for the approximately 100 Cadence customers who visited the team was the upcoming Cadence Help 3.0 release, with its much-enhanced search functionality and improved performance. A big draw was the impressive desk calendar that the visitors could win by correctly answering questions to a quiz based on upcoming Cadence Help functionality. All visitors gained from the live demonstration and preview of the new help functionalities.
Not only was the event a win-win for customers, the Cadence representative teams had much to gain from first-hand views on what customers think about the next planned Cadence Help upgrade, and future online delivery platform the team is targeting. The teams captured customer pulse through an online survey and engaged with experienced and relatively new Cadence product users to fully understand customer requirements in terms of content accessibility, the infrastructure these organizations support, and their overall organizational setup.
Together, the online survey findings and the information gathered by the team through detailed discussions with stakeholders from small and large customer accounts gave a good window to explore what’s possible. The team is now using the collated data to validate their assumptions and plans about future CH upgrades, and is meticulously running through the collated information.
While it wasn’t on the agenda, the team also gathered customer feedback on Cadence content, content delivery and accessibility, and preferences. The team also took the opportunity to educate customers about blogs, more specifically about Virtuosity and Virtuoso Video Diary blogs that are collaboratively being written by the CPG Technical Communications team and other members of the cross-functional teams.
- Rishu Misri Jaggi