The Art of Analog Design Part 1: Overview of Variation-Aware and Robust Design
In this series, we will focus on advanced concepts for custom IC design, in particular, variation-aware design (VAD). With emergence of high-speed simulators such as Spectre® APS, designers can now run...
View ArticleThe Art of Analog Design Part 2: Monte Carlo Sampling
Historically, one of the great challenges that analog and mixed-designers face has been accounting for the effect of process variation on their design. Minimizing the effect of process variation is an...
View ArticleVirtuosity: Driving Along a Longer Route May Take You Home Sooner!
On my way back home every day, I need to make a decision — should I drive less, or more? Because, there are two different routes that I can take to home. The shorter route is usually busier at peak...
View ArticlePhotonics Summit and Workshop 2017
Interested in learning about system-level integration of electronic/photonic devices?The use of silicon photonics allows semiconductor designers to leverage the billions of dollars invested in existing...
View ArticleVirtuoso Video Diary: What Are Parametric Sets?
Over the past few IC6.1.7 and ICADV12.3 ISR releases, a lot of new and useful features have been added to Virtuoso ADE Explorer and Virtuoso ADE Assembler. An interesting one that recently caught my...
View ArticleVirtuosity: Saving, Loading and Sharing ADE Annotation Settings
The whole ADE annotation flow was overhauled way back in IC6.1.6 but at that time there was no way to share the annotation settings between designs, or to automatically load them. Well, in IC6.1.7...
View ArticleVirtuosity: What Color is Your Virtuoso Wearing Today?
Like you, Virtuoso can dress in a different color too every day. Interested to know, how? Read on to find out ....(read more)
View ArticleVirtuosity: Sweeping Multiple Config Views
Before IC6.1.7 ISR10, you could sweep multiple views in ADE for only one block in your design. What if you have more than one block that has multiple views that you want to sweep? Well from ISR10...
View ArticleVirtuosity: Sweeping Multiple DSPF Views in ADE
Wouldn't it be great if you could have a view for your DSPF files and sweep them in an ADE session without having to add them as simulation files? Well now you can! You can create a DSPF view just like...
View ArticleThe Art of Analog Design: Part 3, Monte Carlo Sampling
In Part 2, we looked at Monte Carlo sampling methods. In Part 3, we will consider what happens once Monte Carlo analysis is complete. Of course, we will need to analyze the results, so let’s look at...
View ArticleVirtuosity: Power Filtering!
Finally, we have filters in the Corners Setup form, Results tab, Outputs tab, Data View and Setup assistants in Virtuoso ® ADE Explorer and Virtuoso ® ADE Assembler. But, they are not just for finding...
View ArticleVirtuosity: Can I Speed up My Plots?
If your Virtuoso ® ADE Assembler, Virtuoso ® ADE Explorer or Virtuoso ® ADE XL setup contains multiple sweeps or corner points, or maybe the transient simulations are time consuming, then plotting...
View ArticleThe Art of Analog Design Part 5: Mismatch Analysis II
In Part 4 of the series, we looked at applying mismatch analysis as a design tool. In Part 5, we will continue to look at mismatch analysis by applying the technology to other types of designs..The...
View ArticleThe Art of Analog Design Part 4: Mismatch Analysis
In Part 3, we started to explore how to analyze the results of Monte Carlo analysis. In Part 4, we will consider the question, what is the relationship between process variation and the circuit’s...
View ArticleThe Art of Analog Design Part 5: Response to Frank’s Question
In the comments to blog #5, Frank Wiedmann asked about the correlation between the results of mismatch from Monte Carlo analysis and DC mismatch analysis. It is a fair question and here is a short blog...
View ArticleVirtuosity: Read Mode Done Right
Because of the ease with which you can set up complex sweep, corner and Monte Carlo simulations, the Virtuoso ADE tools are frequently used to perform verification and regression simulation runs. Those...
View ArticleSimplifying the Memory Design Process
On today’s SOC designs, the memory control logics and memory arrays take up a lot of real estate in terms of area and as a part of the larger system since it mostly determines the performance of the...
View ArticleVirtuosity: All New XStream In - The Translation Expressway
A layout design has to go through several iterations and multiple data exchanges across tools for different types of processing during the designing process. At each stage, a large-sized, hierarchical...
View ArticleArt of Analog Design Part 7: Mismatch Tuning
In days of future past, we looked at DC mismatch analysis and compared it to Monte Carlo analysis for analyzing the effect of device mismatch on the offset voltage of a differential amplifier. We found...
View ArticleDealing with AOCVs in SRAMs
Systems on Chip, or SoCs as they’re more commonly called, have become increasingly more complex, and incorporate a dizzying array of functionality to keep up with the evolving trends of technology....
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