On today’s SOC designs, the memory control logics and memory arrays take up a lot of real estate in terms of area and as a part of the larger system since it mostly determines the performance of the application. Regardless of the processors and the interconnect, the memory system provides the instructions and operands and the application cannot be executed any faster than the memory system can handle. Due to this constant demand for increasing memory size for higher performance at advanced nodes, design and verification engineers are faced with multiple challenges.
One of the biggest challenges in memory design is time to market. The designs need to be completed, and ramp to yield, in a very short time frame. But in trying to complete this process, memory designers often face multiple tool and flow challenges as well.
One of the flow challenges is that different tools are used for design, verification and model creation steps. For example, the memory cell design needs very accurate SPICE simulator as well as extensive variation analysis. But how does a designer ensure consistency and accuracy across multiple tools? For example, the FastSPICE tool used to do margin analysis needs to be consistent with the tools or scripts used to generate Liberty timing and power models. These models convey the performance of the memory to the SOC designer, and so it’s very important that they accurately represent the design. So ensuring consistency across the tools and flows makes this process even harder and longer for designers.
Additionally, there is a significant number of PVT corners that designers need to cover as they move to advanced nodes. Our research shows that about 196 PVT corners are needed to accurately characterize the designs at 16nm and below while 12 PVT corners are needed at 90nm. More PVT corners means more verification time, which puts additional pressure on time to market. And finally, while performing memory characterization accurate timing, circuit simulation, power and leakage, and performance metrics must all be met it and currently the only solution is through the use of various point tools. To solve these tool flow challenges, we have created a memory design, verification, and characterization solution. This means that our customers can focus on delivering their memory designs on schedule with the right performance and power, rather than on tools or flows.
The new Cadence® Legato Memory Solution is the industry’s first integrated solution for memory design and verification. It provides a one-stop shop for all memory design, verification and characterization needs, eliminating the complexity of piecing together point tools for multiple design and verification tasks. The Legato Memory Solution delivers up to 2x runtime improvement while meeting demanding design schedules. This solution provides a new standard for completion of memory design on-time and with accuracy.
See also the Breakfast Bytes post Legato: Smooth Memory Design.