By Olivier Arnaud, Product Engineering Group Director, Cadence. Today's complex SoC designs, especially at advanced nodes, significantly increase layout creation and verification time. To meet overall demand for faster design cycle turnaround time, bridge a demand gap, and improve productivity between custom implementation and physical verification tools, Cadence Virtuoso InDesign DRC, part of the overall physical verification portfolio, delivers instant signoff quality design rule checks (DRC) to achieve higher quality layout from the Virtuoso Layout Suite.
Virtuoso InDesign DRC Physical Verification, in conjunction with foundry-certified signoff rule decks with Virtuoso Layout Suite, runs Cadence’s Pegasus Verification System in an instantaneous interactive mode. The Pegasus Verification System is a cloud-ready physical verification signoff solution, which enables engineers to deliver advanced-node integrated circuits (ICs) to market faster.
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