Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?
This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing IR drop and EM currents in the Virtuoso ADE environment. The Spectre EMIR/Voltus-Fi XL flow provides many advanced...
View ArticleVirtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available
The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download at Cadence Downloads.IC6.1.7 ISR23ICADV12.3 ISR23For information on supported platforms, compatibility with...
View ArticleVirtuosity: Saving Time, Effort, and Money with Express Pcells
Use the Express Pcell feature and see for yourself how you can save time, effort, and money!(read more)
View ArticleAccurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures...
In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting is done either to satisfy DRC requirements from foundries to satisfy max. density rule criteria, or to reduce eddy...
View ArticleVirtuosity: Updated ADE Assembler and ADE Explorer Rapid Adoption Kit
The Virtuoso ADE Assembler and Virtuoso ADE Explorer Rapid Adoption Kit (RAK) has been updated for IC6.1.8/ICADVM18.1 to cover the new features. These include Setup Library Assistant Worst Case Corners...
View ArticleAccurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures...
In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting is done either to satisfy DRC requirements from foundries to satisfy max. density rule criteria, or to reduce eddy...
View ArticleVirtuosity: What's New in Run Plan – Part III
After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso ADE Assembler , I am writing this third blog in the series to share with you...
View ArticleSpectre Tech Tips: Optimizing Spectre APS Performance
This blog discusses how to optimize the Spectre APS performance for analog and mixed-signal designs. It introduces the key options for adjusting simulation accuracy and performance, provides solutions...
View ArticleVirtuosity: Introducing the Pin Tool
The Pin Tool follows an object-based approach to working with pins by consolidating and redefining the tasks under one umbrella. Various pin-related tasks are grouped in a logical design flow in the...
View ArticleVirtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction
An important requirement for project sign-off is to ensure that all the design simulations in ADE Assembler are run using the efficient (or pre-defined) sets of operating conditions (corners, sweeps,...
View ArticleVirtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available
The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download. (read more)
View ArticleVirtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further!
Cutting-edge innovation…Top-down planning…Reliableand formalized verification…Scalable performance! These are the current buzzwords floating around in the electronic design automation industry. In...
View ArticleBreak the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET...
How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda of Toshiba Memory (TMC) discloses his recipe today.(read more)
View ArticleVirtuosity: In-design Electromigration Analysis - An efficient way to make...
Shrinking size of ICs with highly complex layouts containing billions of transistors and miles of interconnects....all of this doesn't sound new now. The industry has been pretty fast in adopting...
View ArticleVirtuosity: A Smart Extracted View
The Cadence Quantus Smart View is the next generation of the Extracted View in the Virtuoso environment. The Smart View provides the same functionality as the Extracted View, but it uses a highly...
View ArticleVirtuosity: New Flexible Subwindows
Plots in Cadence Virtuoso Visualization and Analysis can be plotted in a window or subwindow. Subwindows allow you to see plots from different analyses side by side. Until IC6.1.8/ICADVM18.1, the...
View ArticleSpectre Tech Tips: Device Aging? Yes, even Silicon wears out
While most of us would like our electronic gadgets to last forever, the reality is that these gadgets have a lifetime. Most of the time, the lifetime of devices is limited by either mechanical (switch,...
View ArticleSpectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?
This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing IR drop and EM currents in the Virtuoso ADE environment. The Spectre EMIR/Voltus-Fi XL flow provides many advanced...
View ArticleVirtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available
The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download at Cadence Downloads.IC6.1.7 ISR23ICADV12.3 ISR23For information on supported platforms, compatibility with...
View ArticleVirtuosity: Saving Time, Effort, and Money with Express Pcells
Use the Express Pcell feature and see for yourself how you can save time, effort, and money!(read more)
View Article