Analog Behavioral Modeling involves creating models that mimic a desired external circuit behavior at a block level rather than simply reproducing individual transistor characteristics. One of the significant benefits of using models is that they reduce the simulation time. Verilog-A is the most used language by analog designers to describe analog circuit behavior, representing a high-level abstraction of a semiconductor device.
The Verilog-A language is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. It is a sub-set of Verilog-AMS language that has a syntax similar to that of the Verilog-HDL language. With Verilog-A, you can define the top-down system before the actual transistor circuits are assembled. Starting with high-level abstractions, the models become refined as the details become more readily available, and eventually, the system can be evaluated as a whole. For more information, refer to this video on Introduction to Verilog-A Language with a Simple Verilog-A Resistor Model.
Verilog-A has the ability to model a variety of disciplines, the most common of which are electrical, magnetic, thermal, kinematic, and rotational. You can also define your own disciplines. For the most part, the electrical discipline, which is expressed as voltages and currents, is used primarily for integrated circuit modeling. For more information, refer What are Natures and Disciplines in Verilog-A? (Video)
Along with disciplines, there are two modeling approaches in Verilog-A; conservative and signal-flow. The conservative modeling style includes both a potential and a flow to define nodes and branches of a network (electrical system) representing a desired component. In contrast, the signal-flow modeling is useful for high-level modeling or in cases where there is no need to express a current in an electrical discipline. It only has a potential in most cases, thus simulating faster than the conservative model. For more information, refer to this video: What are the Different Types of Analog Systems?
In general, the behavioral analog descriptions of Verilog-A language tend to simulate faster than SPICE transistor-level models, but often at the cost of accuracy. As accuracy is crucial, what do you do to develop the right models matching the transistor-level results?
The direct approach to creating a model is to obtain or calculate the equations that control the device's behavior. You need to know its functionality to write analog behavioral descriptions. Verilog-A encapsulates high-level behavioral descriptions (equations) as well as structural descriptions of systems and components (instantiation of other modules).
If you are wondering how to get started on creating a Verilog-A model from scratch in the text mode from the command-line environment and simulating using the Spectre standalone, then take a look at this video on Creating a Verilog-A Module in the Text Mode from the Command Line. If you want to create a Verilog-A model in the Virtuoso Studio and simulate your models using the ADE Environment, then check out this video on Creating a Verilog-A Module in the Virtuoso Studio .
But what if you don’t know their behavioral descriptions (equations), or they are quite complex to model? How will you calculate them and write your model? Because sometimes, writing behavioral models is not easy if you don’t understand the blocks' functionality. So, another easy way to get your models is to implement it as a lookup table with measured results using the $table_model function in Verilog-A. For more information, look at this video on Using the Verilog-A Table Models.
A detailed behavioral model can be delivered for third-party IP evaluation and reused for validation purposes. But, if you want to encrypt the Verilog-A file or some part of your code for validation, then you can do that using the xmprotect/ncprotect utility. For more information, refer to this video on Encrypting a Verilog-A Source Code using ncprotect/xmprotect utility. So, there are a lot of things you can do with the Verilog-A language.
Related Training Bytes/Videos
What are the major types of Verilog-A models?
What Is a Branch in Verilog-A?
What Are Analog Operators and Filters in Verilog-A?
What are Ports and How to Declare Ports in Verilog-A?
Comparing Contribution and Assignment Operators in Verilog-A
How to Instantiate Verilog-A Modules?
Analog Modeling with Verilog-A (Video)
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