Cadence Online Support
Release Highlights July 2015
Some nice enhancements to the COS experience. Ability to set preferred release for searching, better interface for navigating search results in product manuals.
Using Case Groups: User Roles and Sub-Group
This video shows the functionality provided by Cadence Online Support to share viewing and administering of Cases
Application Notes
Virtuoso Analog Design Environment XL Signals, Expressions, and the Calculator
A "best practices" document covering topics including creating expressions, using the ViVA Calculator, measurements across corners, re-evaluating expressions, and using OCEAN measurement scripts.
What's New in CAT/HED - IC616 ISR12 / ICADV121 ISR14
This document describes what's new in Virtuoso infrastructure in IC 6.1.6 ISR12 (IC6.1.6.500.12).
PVS Multi/Distributed Processing
This document provides introduction and examples of job submission process for multi-processing jobs in PVS.
Pc.db Auto Support for Read-Only Libraries
Documents a new automatic mechanism to update pc.db files for read-only libraries.
Spectre and APS Non-Convergence Debug Guide
Needs no explanation. Just go get it.
Understanding Statistics in PVS DRC Report
The purpose of this document is to explain the meaning of statistics shown in PVS DRC Error report using a simple example. It also touches upon the default display format of the errors in DRC Debug Environment and how to change that default.
Update Training
IC 6.1.6 What's New Library
This is a new initiative across several groups within Cadence to provided a detailed document and videos to overview core new and enhanced features in ISR releases. It covers IC 6.1.6 ISR7 – ISR12. From the COS front page, select Self-Help->Update Training. Bookmark this page to learn about the latest IC Virtuoso release offerings.
Rapid Adoption Kits
PSPICE netlist support in ADE
Spectre supports PSPICE netlist format targeting to include PCB components that are modeled in PSPICE format. This solution does not support PSPICE only designs. A top-level netlist and control statement need to be defined in Spectre, or SPICE format. The recommended approach is to define a subckt in PSPICE netlist format and to instantiate that subckt in a Spectre netlist.
IC6.1 Front to Back Overview (updated for IC6.1.6 ISR12)
What you will learn: Design creation and constraint capture in the Virtuoso Schematic Editor; design analysis and verification with the Analog Design Environment; constraints; Virtuoso environment; buses; constraint aware editing; fluid guardring; Virtuoso spaced-based router; and interactive routing.
Schematic Model Generator (updated for IC6.1.6 ISR12)
Virtuoso Schematic Model Generator (SMG) is tightly integrated into the Virtuoso design environment and enables the generation of analog/mixed-signal behavioral models using a schematic-like representation of the behavioral model. The schematic view is then processed to generate the behavioral model. With this approach, behavioral modeling becomes easier to comprehend, communicate to involved team members, and is better managed compared to manual textual entry.
Videos
Training Bytes
New videos from Cadence training courses on the following topics:
- Virtuoso Connectivity-Driven Layout Transistion
- Using Virtuoso Constraints Effectively
- Virtuoso Space-Based Router
- Physical Verification System
PVS Interactive Short Locator
Two videos—"Finding Shorts" and "Confirming the Cause of Shorts Without Modifying the Layout"
Solutions
Fluid Guard Ring Frequently Asked Questions
You are running simulation using ADE XL environment. While running resource-intensive simulations, if sufficient disk space is not available, you would like to suspend simulations, clean up disk space, and resume them for completion. How can you do this?
Performance Utility to debug Virtuoso Layout Editor performance
How to use the Performance Utility in Virtuoso to debug Virtuoso performance
How to auto update state in ADE L/XL without getting a prompt?
How can I disable the dialog boxes and have the state auto upgrade in background?
How to generate ADE XL datasheet in different format (pdf, svg, etc)?
Describes an environment variable that will allow the waveform snapshots (not the entire datasheet) to be saved in an alternate format for better image resolution.
How to control the number warnings/notes printed on screen and in log file during spectre simulation?
Flexible controls for limiting and filtering warnings and notices from Spectre.
How to change the position of the Direct Plot form on my screen?
You are using ADE L/ADE XL. The Direct Plot form pops-up in the middle of your screen, which is not convenient for you. Is there a way to change the location where Direct Plot form appears?
How to add termMapping for a subcircuit included from ADE model file option during ADE Spectre simulation?
You would like to use external spice or spectre netlist in your ADE spectre simulations. You would be including this external sub-circuit netlist from ADE Model files GUI. Your test bench contains just the ‘symbol’ and ‘spectre’ view of this sub-circuit created by you manually. You have added some ‘save’ statements in ADE outputs by selecting the terminals of the symbol from schematic. When you simulate with ADE spectre, simulation runs fine but your ‘save’ statements are getting ignored and you cannot auto plot any of the terminals of that external spice netlist.
How to disable port order checking for text view vs symbol view?
Your text view port order is different than the symbol view port order for the same cell. You want to disable the port order checking, but still want to check for mismatched pins. And you want to turn off the resulting dialog box that pops up.
New transient analysis memory estimator available
You are simulating large, memory-intensive circuits and would like a "memory estimator" for transient analysis similar to the one already available in hb analysis.
Virtuoso Schematic Editor: Instance objects labels un-selectable
In Virtuoso Schematic Editor window, how can I select Instance-related labels?
How to apply same process variations between two related tests in Virtuoso ADE XL Spectre Monte Carlo analysis?
You are running Monte Carlo simulations with Spectre in Virtuoso ADE XL. You have two or more tests created in your ADE XL setup and would like to apply same process variations to both these tests as these related tests or dependent tests. Starting MMSIM13.1 ISR8, a new Monte Carlo analysis option has been added to Spectre which ensure that same process variations are applied to different netlist/tests.
How to get the path to the netlist directory of each test in Virtuoso ADE XL using SKILL?
How to get the path to the netlist directory of each test from latest run (last history item) in Virtuoso ADE XL using SKILL?
How to set CDF termOrder to be used always, if present, during Netlisting?
You are creating a Spectre netlist from Virtuoso ADE. In the netlist which gets created you see that the CDF termorder is not followed. How can you set CDF termOrder to be followed always, if present?
How can I save selected variables from Verilog-A models?
You have several Verilog-A models in your design, and in order to debug a problem, you'd like to be able to save selected Verilog-A internal variables and plot them after simulation. You are aware that on the Outputs->Save All form you can set saveahdlvars to all but this will require you to save all internal variables from all Verilog-A modules in the design.
Job policy change per ADE XL session
You have multiple ADE XL sessions running. They are all using the same job policy. You notice modifying job policy in one of the ADE XL sessions will change job policy for all ADE XL sessions. You want your changes to the job policy to just affect your current session. How can you do that?
How to correctly set up the command to use in a Virtuoso ADE XL job policy
You wish to use command mode for your job policy—this is where you specify the command used to submit the job using your Distributed Resource Management system rather than using the built-in LBS interface to LSF (from IBM's Platform Computing) or SGE (Sun Grid Engine, or more recently Univa Grid Engine). Is there anything in particular you should take care of when deciding how the job should be submitted?
How to restrict Virtuoso ADE XL ICRP process to run specified number of points?
You have setup Job Policy to run multiple ICRP processes. You would like to run particular number of points with one ICRP. The ICRP process should be killed after running specified number of points and if required start new ICRP process till all points are completed.
Library Manager minimizes rather than exits when the Window Manager X button is pressed
You are using IC616 ISR12 or later (or ICADV12.1 ISR14 or later) and have noticed that when you use the "X" button in the window of the library manager to close it, the library manager minimizes rather than closes. This did not happen in earlier versions. Why is this?
SKILL Information
Refreshed Custom IC Design SKILL Code Library
Custom IC Design SKILL Code Library has been refreshed! This library provides you a set of the most popular SKILL codes to instantly boost your SKILL code examples and enhance your design productivity.