Spectre Tech Tips: How to Improve the Spectre X Simulation Performance

Simulation performance is a critical factor in the time required for chip design, verification, and sign-off. The more efficient the simulations are, the less resources and turnaround time are required for each tapeout. Increasing the awareness among designers on how to optimize the simulation will show a big increase in the design team productivity and efficient use of the design resources from license usage to the computation power requirement.

There is always a tradeoff between simulation accuracy and performance during the design and verification phases. That’s why analog simulators, such as Spectre, Spectre APS, and Spectre X, provide different modes of accuracy to allow designers to use the optimum mode for their testbenches.

As overwhelming as the tradeoff between performance and accuracy could be, Spectre X provides a simple use model to optimize the circuit performance. For new testbenches, you always start with MX preset mode, and move up to AX and then CX if you need more accuracy, and down to LX and then VX if you need more performance.

There are two types of verification tasks: measuring specifications and checking the system behavior or function.

For the task of measuring specifications, one common mistake in which some designs fall is defining accuracy based on the application or the circuit type. However, accuracy is defined mainly by the measurement itself and has less to do with the circuit type, topology, or application. 

Here is an example. Assume that you are designing a ring oscillator and you have different testbenches to test different specifications of the oscillator. First, you start with the frequency of the oscillator at a certain condition and explore the different preset modes of Spectre X to see which mode gives you the accuracy you need for your oscillator.

Based on the results you get in the table, you can derive a conclusion that ring oscillators need AX preset mode to get sufficient accuracy. Is this correct? Wrong! This is only true for measuring the frequency of this ring oscillator. If one of the specifications you are looking for is the current consumption of this block, you will get the following table:

Clearly, if you are creating a testbench to measure only the current consumption of this ring oscillator, VX preset mode will be the optimum mode for accuracy and performance.

In a future blog, we will dive deeper into the accuracy of a simulation and how to adjust it.

For the task of checking system behavior, the behavior of a system can be a sequence of timed events that need to happen in a certain order. In this case, the performance limitation is determined by the signals with the critical timing path and how much tolerance they can withstand. For example, if your system has a startup sequence, to verify this sequence, your simulation performance will be limited by the critical signals order. In most cases, these behavioral or functional verification tasks can be simulated using the most aggressive preset modes like VX.

Here are some tips on how to optimize chip verification or sign-off simulation performance:

1. Adjust the transient analysis stop time to the last measurement event of the testbench. Don’t exceed that. In case the measurement times vary depending on the corners or the circuit conditions, use a Verilog-A code, Spectre MDL script or, .measure statement to stop the simulation once the measurements are achieved.
2. Get the most possible measurements from every testbench.
3. As an exception to the second tip, don’t mix long functional verification runs that require relaxed preset modes with the measurements that require more conservative preset modes. For example, an Xtal oscillator startup time measurement run with noise and jitter measurements.
4. If you are using Virtuoso® ADE Assembler, use the Run Plan feature to first start with the worst case corner run for each measurement before running all other sign-off corners. If the worst case corner fails, you would save the time and resources of running the other corners.
5. Use dummy/empty representation for the blocks that are not involved in the operation for each testbench. This reduces the number of nodes and equations to be solved for the testbench and leads to a shorter run time.
6. If the specifications are measured at specific time periods, use the dynamic parameters feature in the transient analysis to tighten the simulator tolerances (reltol, vabstol, iabstol) during these time periods and relax the tolerances everywhere else.
7. If certain blocks in the system require more conservative tolerances or can withstand relaxed tolerances, use local options to tighten or relax the tolerance levels (reltol, vabstol, iabstol) locally for these blocks.
8. If your testbench includes Verilog-A behavioral models, use the Spectre command-line option -hdllint to enable Verilog-A linter check that will report any accuracy or performance issue due to the Verilog-A models.
9. Pay attention to the Spectre X log file warnings and the Post-Transient Simulation Summary. These are helpful in getting hints about what may potentially affect your simulation performance or cause any convergence difficulties.

In a future blog, we will talk more specifically about a post-layout simulation and how to optimize its accuracy and performance.

Moustafa

Related Resources

• Spectre Classic Simulator, Spectre Accelerated Parallel Simulator (APS), and Spectre Extensive Partitioning Simulator (XPS) User Guide
• Application Note: Introducing Spectre X
• Application Note: Spectre Assert and Design Check Overview

You may also contact your Cadence support AE for guidance.

For more information on Cadence products and services, visit www.cadence.com.

About Spectre Tech Tips

Spectre Tech Tips is a blog series aimed at exploring the capabilities and potential of Spectre simulation platform. In addition to providing insight into the useful features and enhancements in Spectre, this series broadcasts the voice of different bloggers and experts, who share their knowledge and experience on all things related to this platform.