Application Notes
1. Voltus-Fi Power Analysis Support and Power Grid View Generation—Voltus-Fi to Voltus Flow
The Voltus-Fi to Voltus flow provides the complete Cadence power integrity solution for full-chip power integrity analysis for all designs, featuring accurate transistor EMIR analysis and high-quality analog IP grid modeling. This application note covers the process of Voltus-Fi flow based on the 28nm process, Power Grid View generation, and on using Voltus-Fi-generated PGVs for Voltus full-chip level SoC power signoff.
2. Annotation Browser—Quick Start Guide
The Annotation Browser assistant enables you to view, locate, and manage the violation markers generated in the current design by different Virtuoso applications. This document helps you get started with the Annotation Browser assistant in the Virtuoso backend flow.
3. Spectre PSPICE Netlist Support
Spectre now enables the user to include PCB components in PSPICE format into a Spectre integrated circuit simulation. The solution is based on the approach of using a regular Spectre simulation including the Spectre simulator control statements, but additionally allowing to include user define subcircuits in PSPICE format.
An overview of a new way to create arrays using Generate Selected From Source
Rapid Adoption Kits
5. Introduction to AMS Designer Simulation (updated for IC6.1.6 ISR6 and INCISIV 13.2)
This material uses a simple database consisting of an inverter chain to show the setup and use of AMS Designer. Both the GUI-driven flow with ADE L and the text-based command line flow are shown.
6. IC6.1.6 Rapid Analog Prototyping (RAP) Workshop
This is a front-to-back flow that uses the Virtuoso Constraint System to generate the layout of an analog circuit in an automated manner, in order to obtain early feedback on parasitics and device effects on circuit simulation. The basic design goals and requirements are captured through a set of constraints in the schematic, which are implemented in the layout through automatic placement and routing. The resultant LVS clean layout is then extracted, and the circuit re-simulated using the extracted data. The circuit designer can thus identify issues early on and make necessary changes to quickly iterate through the flow, which helps avoid costly changes late in the cycle and enables faster design convergence.
Also provides pointers to Application Notes on "Using the Virtuoso Constraint System for Layout Automation for Rapid Prototyping" and "Circuit Prospecter in Virtuoso (IC6.1.5/6.1.6): An Overview"
7. Understanding CDF for Operating Point & Model Parameter Annotation
The Component Description Format (CDF) describes the parameters and the attributes of parameters of individual components and libraries of components. The CDF lets you create and describe your own components. A CDF description assigns parameters and parameter attributes to libraries and cells for many purposes:
- Assigning parameter names and values
- Allocating units and default values
- Checking that values lie within specified ranges
- Dynamically changing how parameters are displayed depending on predefined conditions
- Executing a SKILL callback function whenever certain information is changed
Videos
8. Training Bytes videos from the Virtuoso Layout Pro course
9. Virtuoso Layout Suite: Label Update feature
Label Update feature allows the designer to quickly and intuitively modify Pin Labels and Text Labels to make them readable and aesthetic, making easier to work on the design.
Describes how to place I/O pins generated by LayoutXL's Generate All From Source command to the location of instance pins.
11. Understanding the GDS Merge Flow in XStream
This video shows how multiple GDS files are merged during XStream translation in different scenarios.
Solutions
12. Abstract Generator FinFET support in ICADV12.1 release
How does Abstract Generator handle ANTENNAGATEAREA extraction for FinFETs?