Happy New Year to all from the award-winning Virtuosity blog team (Alice, Praveena, Rajesh and myself)! Okay, so it was an internal Cadence Standing Ovation Team Award, but it works for me.
There are few things I love more than learning and every month (or two) when I look through the new content, I am delighted to see how much high-quality material is available to highlight new features and help you use our software more effectively.
So without further ado...
1. Cadence Online Support Release Highlights: December 22, 2014
Application Notes
2. FGR Object Oriented Infrastructure: Class Hierarchy and Extensibility
The implementation of the Fluid Guard Ring solution resides in a SKILL object-oriented infrastructure. This consists of classes and their methods known as Virtuoso Fluid Object (VFO). The VFO infrastructure comprises specific class declarations that have a defined hierarchy. This document covers information about these classes, as well as information on how to define custom FGR PCell devices in the technology file.
3. Statistical Analysis Quick Start ADE XL/GXL
Monte Carlo sampling setup and post-processing, statistical corners, mismatch and variance contribution in ADE XL/GXL updated for IC6.1.6 ISR9 and ICADV12.1 ISR11.
4. What is New in Virtuoso Front End IC6.1.6 ISR9 and ICADV12.1 ISR11
New features in ADE L/XL/GXL and ViVA in Virtuoso IC6.1.6 ISR9 and ICADV12.1 ISR11.
5. Waveform Data Reduction and Compression Techniques
This document explores the various options available to analog/mixed-signal designers to reduce the waveform dump size and some post-processing techniques in the waveform viewers to improve the waveform viewing experience.
6. Virtuoso Stream Translator Enhancements in IC6.1.6 ISR9
Describes performance and usability improvements of Stream translation in Virtuoso IC6.1.6ISR9.
7. Analyzing XStream Performance Issues
This application note explains how to understand and improve runtime of Virtuoso streamIn and streamOut.
8. VLS XL - Extractor Verify substrate connectivity
VLS XL Connectivity Extractor supports the mature process nodes as well as the advanced process nodes (10nm, 14nm FDSOI...). This document provides guidelines on how to write the techfile in order to verify the substrate connectivity.
Videos
9. Removing Devices from Netlists
This video illustrates the different methods of removing devices from the netlist of a design, which is generated using an OSS-based netlister.
10. Automatic Extraction of Power Intent Using PIEA
This video shows using the Power Intent Extraction Options form for automatic extraction of power intent.
11. Job Policy Setup for Distributed Processing in ADE XL
This video demonstrates how to set job policy for distributed processing in ADE XL with LSF. It has been developed on IC6.1.6 ISR9.
12. Virtuoso Layout Suite: Improve hierarchical design editing performance using Area Display feature
Improve hierarchical design editing performance using the Area Display feature.
13. Out of Context Probing and Plotting in ADE L and ADE XL
Demonstrates how to do out-of-context probing from ADE.
This video provides an overview of DRD Compactor options.
15. Result Annotation Flow Enhancement in Virtuoso
This video demonstrates annotation set up revamp in IC 6.1.6, access of annotation, and the plotting menu from schematic editor and the annotation setup form.
16. Communication of SMG with VSE and amsDmv
Demonstrates SMG VSE sub-app feature and SMG-amsDmv Communication feature.
17. Comparing Constraints Between Schematic and Layout
This video illustrates how to open a constraint comparison report and use it.
In this video, you will learn how to characterize mixed signal blocks using Liberate AMS and generate a Liberty library (.lib) to enable timing, power, and noise signoff for a full chip including mixed-signal blocks.
19. Using Design Rule Driven Editing
Provides an overview of the various DRD modes.
Rapid Adoption Kits (RAKs)
20. PVS Interactive Short Locator
PVS Interactive Short Locator in PVS 14.1. This is a workshop on the PVS Interactive Short Locator Application. This is designed to help new users learn and use LVS shorts debugging feature more effectively.
21. Virtuoso IPVS
Virtuoso IPVS in IC616 ISR9 / ICADV 12.1 ISR11 / PVS 14.1. Virtuoso IPVS is a mechanism where the PVS verification tool is tightly integrated with the Virtuoso platform. Virtuoso IPVS uses foundry-supplied signoff rules to verify your design.
22. PVS Configurator
PVS Configurator in PVS 14.1. Using configuration files and letting the designers make choices and save them for subsequent runs is an effective way to provide the options to the designer. Using a configuration file also lets the designers choose options directly from the main rule file supplied by the foundry.
Solutions
23. Spectre, SpectreRF, AMS-D, XPS, and APS feature/license matrix for MMSIM 14.1
Explains the number of MMSIM tokens needed for various new analyses and options for Spectre, SpectreRF, AMS-D, XPS, and APS.
24. Need to update license server version for MMSIM 14.1
What to do if MMSIM 14.1 hangs waiting for a license.
25. Distributed processing using SKILL script
IPC commands such as ipcBeginProcess are typically used for generating child processes that execute third-party tools. It is actually also possible to use IPC commands to distribute repetitive SKILL tasks (e.g., flattening of a cell) so as to significantly reduce the total run time. Includes a detailed example.
26. How to create a via which uses a layer purpose other than drawing
The OpenAccess database does not support layer purposes in case of standardViaDef. Hence it is not possible to have purpose specific standard via. You can use a cdsVia which supports layer purpose. The cdsVia can be defined in the devices section of the technology file or library.
Training Bytes
More short video clips from Cadence Training courses:
- PVS14.1
- Virtuoso Schematic Editor
- Using Virtuoso Constraints Effectively
- Virtuoso Layout Suites Update Training
- Virtuoso Layout Design Basics
- Virtuoso Space-based Router
- SKILL Language Programming Introduction
Training Bytes videos can now be accessed directly from the Resources->Self Learning Library page on http://support.cadence.com.