Application Notes
1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40) LVS
Shows you how to put in place the PVS(LVS)-QRC(av_extracted) view using TSMC files.
Videos
2. Mismatch Contribution in Virtuoso Analog Design Environment GXL
Mismatch contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify the identified devices in the design to make the design less sensitive to device mismatch variation in IC 6.1.6.
Rapid Adoption Kits
3. Substrate/Well Connectivity Extraction
The substrate/well connectivity enhancements were made in VLS XL to help designers work more effectively on designs at lower geometry nodes.This RAK steps through the Extractor capabilities -- detecting short on a same substrate, creating isolated substrate and how to break a propagated connectivity on the same layer based on a generic 90nm PDK. IC6.1.6 ISR5
4. Making a layout XL-compliant using Update Binding (XLME)
Often layout engineers have existing or legacy layouts that they wish to use in VLS XL to take advantage of the connectivity-driven flow. With the introduction of the Update Binding functionality in IC6.1.6, it is now possible to quickly make a legacy layout fully XL-compliant. IC6.1.6 ISR6.
5. Routing Constraint Interoperability - AoT Flow (Analog on Top)
This workshop demonstrates the capability to capture routing constraints in either Virtuoso or Encounter Digital Implementation System, propagate routing constraints across hierarchical boundaries, perform routing (using NanoRoute and the Virtuoso Wire Editor) while honoring constraints, and validate the routing results against the original routing constraints using PVS-cv. EDI 13.2 and Virtuoso IC6.1.5 ISR17.
The Custom Digital Placer is used to implement small digital designs with several thousand placeable components. The Custom Digital Placer can also be used to place a few transistor-level devices along with standard cells (mixed mode). IC6.1.6 ISR6
7. IC6.1.6 VSR ASIC Power and Signal Block-Level Autorouting Flow
This RAK steps through the power routing and signal routing of block-level stdcell ASIC flow. IC6.1.6 ISR6.
This RAK steps thorugh the Floorplanner Flow in Virtuoso IC6.1.6 ISR5. The objective of this flow is to increase layout productivity through improved floorplanner functionality aimed at block-level interconnect.
9. Virtuoso Analog Auto Placer
This RAK demonstrates the steps to use the Analog Placer in Virtuoso IC6.1.6 ISR5. This does automatic constraint-based placement. We will explore different placement modes like Quick Placement, Automatic Placement (more compact), and Place Like Schematic.
10. Voltus-Fi EMIR Analysis Workshop
This workshop will take you through IR-drop and electromigration analysis flow utilizing our patent-pending technology in MMSIM (APS/XPS) followed by visualization of results in Virtuoso Layout Editor. IC6.1.6 ISR6 and MMSIM13.1 ISR3.
This RAK steps through the pcell abutment in Virtuoso IC6.1.6 ISR6.The objective of this document is to illustrate setting up the pcell abutment using the different properties with Cadence default abutment code and using custom abutment function.
Blogs
12. High-Yield Analysis and Optimization -- How to Design the Circuit to Six Sigma
Discusses the methodology and algorithms in ADE GXL to perform high-yield estimation and six-sigma statistical corner creation to help meet high-yield requirements for memory design and other mission-critical applications.
13. How to Specify Phase Noise as an Instance Parameter in Spectre Sources (e.g. vsource, isource, Port)
Describes the new capability in MMISM 13.1 to specify phase noise as an instance parameter on Spectre sources.
14. DAC 2014: 30+ Customer, Partner Presentations Now Available on Cadence.com
One of the busiest spots on the Design Automation Conference (DAC 2014) show floor was the Cadence Theater, which featured continuous customer and partner presentations over a three-day period June 2-4. These informal, half-hour presentations allowed engineers to learn about problems and solutions from other engineers, and to hear about the latest capabilities from Cadence ecosystem partners. Most of the Cadence Theater presentations are now available in the form of audiotapes and slides.
Solutions
15. How to stop popup of Distributed Processing Options Form
For users of ADE Distributed Processing, a few key environment variables for those popup haters out there.
16. Information, Q&A on APS parasitic reduction: +parasitics and ++parasitics options
Nice one-stop shop for information about what these options do and how to use them.
17. How is mismatch applied in array/parallel devices in Spectre Monte Carlo?
Important information about the way mismatch is handled for different types of device configurations.
18. How to perform a stability (stb) analysis on a loop within an extracted view
Clever little trick to facilitate analyzing loop stability on post-layout designs.
19. Verilog Netlisting (Verilog Out): Quick Reference to Basics and Frequently Referred Solutions
Handy document on Verilog netlisting with lots of useful links to extra information.
20. auCdl Netlisting of schematic: Quick Reference to Basics and Frequently Referred Solutions
Handy document on auCdl netlisting, usually used for LVS. Lots of links to extra information.
21. SPICEIN: Quick Reference to Basics and Frequently Referred Solutions
Handy document on SpiceIn to import textual netlists (CDL, HSpice, Spectre, SPICE) and create either schematic or netlist views.
Stacy Whiteman