I'll confess: I didn't learn all of this strictly by browsing http://support.cadence.com (Cadence Online Support). I also wandered over onto http://www.cadence.com/community/blogs/ii (Industry Insights blog) and http://www.cadence.com/cadence/events (Cadence Events), which were well worth a look.
ApplicationNote
You've gotta love any technical document that begins with the word "demystifying". Explains typical causes of and solutions for elaboration errors frequently encountered in running a digital or mixed-signal design using AMS Designer. Organized by error code. Includes descriptions, examples, solutions, and accompanying database.
Videos
2. Running Monte-Carlo Simulations with AMS in ADE-XL
Computer-narrated video describing how to set up and run Monte Carlo simulations using the AMS simulator in ADE XL
3. Virtuoso Connectivity-Driven Layout Solution Segment--Connectivity Extraction from Labels
Video segment from a Cadence physical design training course demonstrating extracting connectivity from labels
Blog
4. CDNLive Silicon Valley 2013 Proceedings Available for Download
Over 80 downloadable presentations from customers and partners discussing how they have used Cadence tools to solve real problems. Custom IC, mixed signal, low power, advanced node--you name it, you can find something interesting to learn about.
Rapid Adoption Kit
5. Digital Mixed-Signal (DMS) Implementation Using EDI and Virtuoso
Reaching out to our colleagues in the digital world. Learn about design import, early timing analysis, pin optimization, AoT block design, and top-level timing analysis. Includes database and detailed workshop instructions.
Webinars
6. TSMC-Cadence Webinars for Advanced Node Design: Addressing Layout-Dependent Effects
Archived webinar discussing the TSMC Custom Design Reference Flow 3.0, which provides a complete layout-dependent effect (LDE) flow for circuit and layout designers working at 28nm and below.
7. A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence Tools
Upcoming webinar scheduled for May 23, 2013. Learn about how in-design design rule checking (DRC) and double patterning technology (DPT) checking can improve productivity; how to efficiently manage coloring data in front-to-back custom design flows; how local interconnect layers are supported within the Cadence Virtuoso platform, and how TSMC’s 20nm process technology and the Cadence methodology support this process.
Solutions
8. Recommended platform patches for systems running Cadence products
Not much description needed for this one. Always a handy table of information to have.
9. Fluid Guardring changes shape with newer version of Virtuoso
How to prevent Fluid Guardrings from changing shapes and spacings with changes to your Virtuoso version.
10. How to keep ADE XL jobs running even if ADE XL GUI crashes
New environment variable in ADE XL, which allows you to close the ADE XL or Virtuoso session without killing jobs that are currently running. Also works if Virtuoso crashes.